49 	const struct dpll_data *dd;  in _omap3_dpll_write_clken()  local
52 	dd = clk->dpll_data;  in _omap3_dpll_write_clken()
54 	v = ti_clk_ll_ops->clk_readl(&dd->control_reg);  in _omap3_dpll_write_clken()
55 	v &= ~dd->enable_mask;  in _omap3_dpll_write_clken()
56 	v |= clken_bits << __ffs(dd->enable_mask);  in _omap3_dpll_write_clken()
57 	ti_clk_ll_ops->clk_writel(v, &dd->control_reg);  in _omap3_dpll_write_clken()
63 	const struct dpll_data *dd;  in _omap3_wait_dpll_status()  local
68 	dd = clk->dpll_data;  in _omap3_wait_dpll_status()
71 	state <<= __ffs(dd->idlest_mask);  in _omap3_wait_dpll_status()
73 	while (((ti_clk_ll_ops->clk_readl(&dd->idlest_reg) & dd->idlest_mask)  in _omap3_wait_dpll_status()
140 	const struct dpll_data *dd;  in _omap3_noncore_dpll_lock()  local
147 	dd = clk->dpll_data;  in _omap3_noncore_dpll_lock()
148 	state <<= __ffs(dd->idlest_mask);  in _omap3_noncore_dpll_lock()
151 	if ((ti_clk_ll_ops->clk_readl(&dd->idlest_reg) & dd->idlest_mask) ==  in _omap3_noncore_dpll_lock()
304 	struct dpll_data *dd = clk->dpll_data;  in omap3_noncore_dpll_program()  local
317 		v = ti_clk_ll_ops->clk_readl(&dd->control_reg);  in omap3_noncore_dpll_program()
318 		v &= ~dd->freqsel_mask;  in omap3_noncore_dpll_program()
319 		v |= freqsel << __ffs(dd->freqsel_mask);  in omap3_noncore_dpll_program()
320 		ti_clk_ll_ops->clk_writel(v, &dd->control_reg);  in omap3_noncore_dpll_program()
324 	v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);  in omap3_noncore_dpll_program()
327 	if (dd->dcc_mask) {  in omap3_noncore_dpll_program()
328 		if (dd->last_rounded_rate >= dd->dcc_rate)  in omap3_noncore_dpll_program()
329 			v |= dd->dcc_mask; /* Enable DCC */  in omap3_noncore_dpll_program()
331 			v &= ~dd->dcc_mask; /* Disable DCC */  in omap3_noncore_dpll_program()
334 	v &= ~(dd->mult_mask | dd->div1_mask);  in omap3_noncore_dpll_program()
335 	v |= dd->last_rounded_m << __ffs(dd->mult_mask);  in omap3_noncore_dpll_program()
336 	v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask);  in omap3_noncore_dpll_program()
339 	if (dd->dco_mask) {  in omap3_noncore_dpll_program()
340 		_lookup_dco(clk, &dco, dd->last_rounded_m, dd->last_rounded_n);  in omap3_noncore_dpll_program()
341 		v &= ~(dd->dco_mask);  in omap3_noncore_dpll_program()
342 		v |= dco << __ffs(dd->dco_mask);  in omap3_noncore_dpll_program()
344 	if (dd->sddiv_mask) {  in omap3_noncore_dpll_program()
345 		_lookup_sddiv(clk, &sd_div, dd->last_rounded_m,  in omap3_noncore_dpll_program()
346 			      dd->last_rounded_n);  in omap3_noncore_dpll_program()
347 		v &= ~(dd->sddiv_mask);  in omap3_noncore_dpll_program()
348 		v |= sd_div << __ffs(dd->sddiv_mask);  in omap3_noncore_dpll_program()
370 	ti_clk_ll_ops->clk_writel(v, &dd->mult_div1_reg);  in omap3_noncore_dpll_program()
373 	if (dd->m4xen_mask || dd->lpmode_mask) {  in omap3_noncore_dpll_program()
374 		v = ti_clk_ll_ops->clk_readl(&dd->control_reg);  in omap3_noncore_dpll_program()
376 		if (dd->m4xen_mask) {  in omap3_noncore_dpll_program()
377 			if (dd->last_rounded_m4xen)  in omap3_noncore_dpll_program()
378 				v |= dd->m4xen_mask;  in omap3_noncore_dpll_program()
380 				v &= ~dd->m4xen_mask;  in omap3_noncore_dpll_program()
383 		if (dd->lpmode_mask) {  in omap3_noncore_dpll_program()
384 			if (dd->last_rounded_lpmode)  in omap3_noncore_dpll_program()
385 				v |= dd->lpmode_mask;  in omap3_noncore_dpll_program()
387 				v &= ~dd->lpmode_mask;  in omap3_noncore_dpll_program()
390 		ti_clk_ll_ops->clk_writel(v, &dd->control_reg);  in omap3_noncore_dpll_program()
440 	struct dpll_data *dd;  in omap3_noncore_dpll_enable()  local
443 	dd = clk->dpll_data;  in omap3_noncore_dpll_enable()
444 	if (!dd)  in omap3_noncore_dpll_enable()
460 	if (clk_hw_get_rate(hw) == clk_hw_get_rate(dd->clk_bypass)) {  in omap3_noncore_dpll_enable()
461 		WARN_ON(parent != dd->clk_bypass);  in omap3_noncore_dpll_enable()
464 		WARN_ON(parent != dd->clk_ref);  in omap3_noncore_dpll_enable()
503 	struct dpll_data *dd;  in omap3_noncore_dpll_determine_rate()  local
508 	dd = clk->dpll_data;  in omap3_noncore_dpll_determine_rate()
509 	if (!dd)  in omap3_noncore_dpll_determine_rate()
512 	if (clk_hw_get_rate(dd->clk_bypass) == req->rate &&  in omap3_noncore_dpll_determine_rate()
513 	    (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {  in omap3_noncore_dpll_determine_rate()
514 		req->best_parent_hw = dd->clk_bypass;  in omap3_noncore_dpll_determine_rate()
518 		req->best_parent_hw = dd->clk_ref;  in omap3_noncore_dpll_determine_rate()
565 	struct dpll_data *dd;  in omap3_noncore_dpll_set_rate()  local
572 	dd = clk->dpll_data;  in omap3_noncore_dpll_set_rate()
573 	if (!dd)  in omap3_noncore_dpll_set_rate()
576 	if (clk_hw_get_parent(hw) != dd->clk_ref)  in omap3_noncore_dpll_set_rate()
579 	if (dd->last_rounded_rate == 0)  in omap3_noncore_dpll_set_rate()
584 		freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n);  in omap3_noncore_dpll_set_rate()
644 	const struct dpll_data *dd;  in omap3_dpll_autoidle_read()  local
650 	dd = clk->dpll_data;  in omap3_dpll_autoidle_read()
652 	if (!dd->autoidle_mask)  in omap3_dpll_autoidle_read()
655 	v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg);  in omap3_dpll_autoidle_read()
656 	v &= dd->autoidle_mask;  in omap3_dpll_autoidle_read()
657 	v >>= __ffs(dd->autoidle_mask);  in omap3_dpll_autoidle_read()
673 	const struct dpll_data *dd;  in omap3_dpll_allow_idle()  local
679 	dd = clk->dpll_data;  in omap3_dpll_allow_idle()
681 	if (!dd->autoidle_mask)  in omap3_dpll_allow_idle()
689 	v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg);  in omap3_dpll_allow_idle()
690 	v &= ~dd->autoidle_mask;  in omap3_dpll_allow_idle()
691 	v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);  in omap3_dpll_allow_idle()
692 	ti_clk_ll_ops->clk_writel(v, &dd->autoidle_reg);  in omap3_dpll_allow_idle()
703 	const struct dpll_data *dd;  in omap3_dpll_deny_idle()  local
709 	dd = clk->dpll_data;  in omap3_dpll_deny_idle()
711 	if (!dd->autoidle_mask)  in omap3_dpll_deny_idle()
714 	v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg);  in omap3_dpll_deny_idle()
715 	v &= ~dd->autoidle_mask;  in omap3_dpll_deny_idle()
716 	v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);  in omap3_dpll_deny_idle()
717 	ti_clk_ll_ops->clk_writel(v, &dd->autoidle_reg);  in omap3_dpll_deny_idle()
756 	const struct dpll_data *dd;  in omap3_clkoutx2_recalc()  local
769 	dd = pclk->dpll_data;  in omap3_clkoutx2_recalc()
771 	WARN_ON(!dd->enable_mask);  in omap3_clkoutx2_recalc()
773 	v = ti_clk_ll_ops->clk_readl(&dd->control_reg) & dd->enable_mask;  in omap3_clkoutx2_recalc()
774 	v >>= __ffs(dd->enable_mask);  in omap3_clkoutx2_recalc()
775 	if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE))  in omap3_clkoutx2_recalc()
792 	struct dpll_data *dd;  in omap3_core_dpll_save_context()  local
795 	dd = clk->dpll_data;  in omap3_core_dpll_save_context()
797 	v = ti_clk_ll_ops->clk_readl(&dd->control_reg);  in omap3_core_dpll_save_context()
798 	clk->context = (v & dd->enable_mask) >> __ffs(dd->enable_mask);  in omap3_core_dpll_save_context()
801 		v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);  in omap3_core_dpll_save_context()
802 		dd->last_rounded_m = (v & dd->mult_mask) >>  in omap3_core_dpll_save_context()
803 						__ffs(dd->mult_mask);  in omap3_core_dpll_save_context()
804 		dd->last_rounded_n = ((v & dd->div1_mask) >>  in omap3_core_dpll_save_context()
805 						__ffs(dd->div1_mask)) + 1;  in omap3_core_dpll_save_context()
821 	const struct dpll_data *dd;  in omap3_core_dpll_restore_context()  local
824 	dd = clk->dpll_data;  in omap3_core_dpll_restore_context()
830 		v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);  in omap3_core_dpll_restore_context()
831 		v &= ~(dd->mult_mask | dd->div1_mask);  in omap3_core_dpll_restore_context()
832 		v |= dd->last_rounded_m << __ffs(dd->mult_mask);  in omap3_core_dpll_restore_context()
833 		v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask);  in omap3_core_dpll_restore_context()
834 		ti_clk_ll_ops->clk_writel(v, &dd->mult_div1_reg);  in omap3_core_dpll_restore_context()
853 	struct dpll_data *dd;  in omap3_noncore_dpll_save_context()  local
856 	dd = clk->dpll_data;  in omap3_noncore_dpll_save_context()
858 	v = ti_clk_ll_ops->clk_readl(&dd->control_reg);  in omap3_noncore_dpll_save_context()
859 	clk->context = (v & dd->enable_mask) >> __ffs(dd->enable_mask);  in omap3_noncore_dpll_save_context()
862 		v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);  in omap3_noncore_dpll_save_context()
863 		dd->last_rounded_m = (v & dd->mult_mask) >>  in omap3_noncore_dpll_save_context()
864 						__ffs(dd->mult_mask);  in omap3_noncore_dpll_save_context()
865 		dd->last_rounded_n = ((v & dd->div1_mask) >>  in omap3_noncore_dpll_save_context()
866 						__ffs(dd->div1_mask)) + 1;  in omap3_noncore_dpll_save_context()
882 	const struct dpll_data *dd;  in omap3_noncore_dpll_restore_context()  local
885 	dd = clk->dpll_data;  in omap3_noncore_dpll_restore_context()
887 	ctrl = ti_clk_ll_ops->clk_readl(&dd->control_reg);  in omap3_noncore_dpll_restore_context()
888 	mult_div1 = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);  in omap3_noncore_dpll_restore_context()
890 	if (clk->context == ((ctrl & dd->enable_mask) >>  in omap3_noncore_dpll_restore_context()
891 			     __ffs(dd->enable_mask)) &&  in omap3_noncore_dpll_restore_context()
892 	    dd->last_rounded_m == ((mult_div1 & dd->mult_mask) >>  in omap3_noncore_dpll_restore_context()
893 				   __ffs(dd->mult_mask)) &&  in omap3_noncore_dpll_restore_context()
894 	    dd->last_rounded_n == ((mult_div1 & dd->div1_mask) >>  in omap3_noncore_dpll_restore_context()
895 				   __ffs(dd->div1_mask)) + 1) {  in omap3_noncore_dpll_restore_context()
987 	struct dpll_data *dd;  in omap3_dpll5_apply_errata()  local
1001 	dd = clk->dpll_data;  in omap3_dpll5_apply_errata()
1002 	dd->last_rounded_m = d->m;  in omap3_dpll5_apply_errata()
1003 	dd->last_rounded_n = d->n;  in omap3_dpll5_apply_errata()
1004 	dd->last_rounded_rate = div_u64((u64)parent_rate * d->m, d->n);  in omap3_dpll5_apply_errata()