Lines Matching refs:TI_CLK_GATE

286 	{ 8, TI_CLK_GATE, dra7_dss_dss_clk_parents, NULL },
287 	{ 9, TI_CLK_GATE, dra7_dss_48mhz_clk_parents, NULL },
288 	{ 10, TI_CLK_GATE, dra7_dss_hdmi_clk_parents, NULL },
289 	{ 11, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
290 	{ 12, TI_CLK_GATE, dra7_dss_video1_clk_parents, NULL },
291 	{ 13, TI_CLK_GATE, dra7_dss_video2_clk_parents, NULL },
343 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
360 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
372 	{ 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
382 	{ 8, TI_CLK_GATE, dra7_sata_ref_clk_parents, NULL },
387 	{ 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
415 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
416 	{ 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
417 	{ 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
422 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
423 	{ 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
424 	{ 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
506 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
511 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
516 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
521 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
526 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
531 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
536 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
551 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
568 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
776 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },