Lines Matching refs:TI_CLK_GATE

232 	{ 8, TI_CLK_GATE, dra7_dss_dss_clk_parents, NULL },
233 	{ 9, TI_CLK_GATE, dra7_dss_48mhz_clk_parents, NULL },
234 	{ 10, TI_CLK_GATE, dra7_dss_hdmi_clk_parents, NULL },
235 	{ 11, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
236 	{ 12, TI_CLK_GATE, dra7_dss_video1_clk_parents, NULL },
237 	{ 13, TI_CLK_GATE, dra7_dss_video2_clk_parents, NULL },
264 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
281 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
293 	{ 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
303 	{ 8, TI_CLK_GATE, dra7_sata_ref_clk_parents, NULL },
318 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
319 	{ 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
320 	{ 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
325 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
326 	{ 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
327 	{ 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
353 	{ 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
419 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
424 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
429 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
434 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
439 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
459 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
464 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
479 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
496 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
674 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },