Lines Matching +full:clock +full:- +full:name
14 #include <linux/clk-provider.h>
186 const char *name; in ti_adpll_clk_get_name() local
190 err = of_property_read_string_index(d->np, in ti_adpll_clk_get_name()
191 "clock-output-names", in ti_adpll_clk_get_name()
193 &name); in ti_adpll_clk_get_name()
197 name = devm_kasprintf(d->dev, GFP_KERNEL, "%08lx.adpll.%s", in ti_adpll_clk_get_name()
198 d->pa, postfix); in ti_adpll_clk_get_name()
201 return name; in ti_adpll_clk_get_name()
206 static int ti_adpll_setup_clock(struct ti_adpll_data *d, struct clk *clock, in ti_adpll_setup_clock() argument
207 int index, int output_index, const char *name, in ti_adpll_setup_clock() argument
214 d->clocks[index].clk = clock; in ti_adpll_setup_clock()
215 d->clocks[index].unregister = unregister; in ti_adpll_setup_clock()
218 postfix = strrchr(name, '.'); in ti_adpll_setup_clock()
221 dev_warn(d->dev, "clock %s con_id lookup may fail\n", in ti_adpll_setup_clock()
222 name); in ti_adpll_setup_clock()
223 snprintf(con_id, 16, "pll%03lx%s", d->pa & 0xfff, postfix + 1); in ti_adpll_setup_clock()
224 cl = clkdev_create(clock, con_id, NULL); in ti_adpll_setup_clock()
226 return -ENOMEM; in ti_adpll_setup_clock()
227 d->clocks[index].cl = cl; in ti_adpll_setup_clock()
229 dev_warn(d->dev, "no con_id for clock %s\n", name); in ti_adpll_setup_clock()
235 d->outputs.clks[output_index] = clock; in ti_adpll_setup_clock()
236 d->outputs.clk_num++; in ti_adpll_setup_clock()
243 int output_index, char *name, in ti_adpll_init_divider() argument
251 struct clk *clock; in ti_adpll_init_divider() local
253 child_name = ti_adpll_clk_get_name(d, output_index, name); in ti_adpll_init_divider()
255 return -EINVAL; in ti_adpll_init_divider()
258 clock = clk_register_divider(d->dev, child_name, parent_name, 0, in ti_adpll_init_divider()
260 &d->lock); in ti_adpll_init_divider()
261 if (IS_ERR(clock)) { in ti_adpll_init_divider()
262 dev_err(d->dev, "failed to register divider %s: %li\n", in ti_adpll_init_divider()
263 name, PTR_ERR(clock)); in ti_adpll_init_divider()
264 return PTR_ERR(clock); in ti_adpll_init_divider()
267 return ti_adpll_setup_clock(d, clock, index, output_index, child_name, in ti_adpll_init_divider()
273 char *name, struct clk *clk0, in ti_adpll_init_mux() argument
280 struct clk *clock; in ti_adpll_init_mux() local
282 child_name = ti_adpll_clk_get_name(d, -ENODEV, name); in ti_adpll_init_mux()
284 return -ENOMEM; in ti_adpll_init_mux()
287 clock = clk_register_mux(d->dev, child_name, parents, 2, 0, in ti_adpll_init_mux()
288 reg, shift, 1, 0, &d->lock); in ti_adpll_init_mux()
289 if (IS_ERR(clock)) { in ti_adpll_init_mux()
290 dev_err(d->dev, "failed to register mux %s: %li\n", in ti_adpll_init_mux()
291 name, PTR_ERR(clock)); in ti_adpll_init_mux()
292 return PTR_ERR(clock); in ti_adpll_init_mux()
295 return ti_adpll_setup_clock(d, clock, index, -ENODEV, child_name, in ti_adpll_init_mux()
301 int output_index, char *name, in ti_adpll_init_gate() argument
309 struct clk *clock; in ti_adpll_init_gate() local
311 child_name = ti_adpll_clk_get_name(d, output_index, name); in ti_adpll_init_gate()
313 return -EINVAL; in ti_adpll_init_gate()
316 clock = clk_register_gate(d->dev, child_name, parent_name, 0, in ti_adpll_init_gate()
318 &d->lock); in ti_adpll_init_gate()
319 if (IS_ERR(clock)) { in ti_adpll_init_gate()
320 dev_err(d->dev, "failed to register gate %s: %li\n", in ti_adpll_init_gate()
321 name, PTR_ERR(clock)); in ti_adpll_init_gate()
322 return PTR_ERR(clock); in ti_adpll_init_gate()
325 return ti_adpll_setup_clock(d, clock, index, output_index, child_name, in ti_adpll_init_gate()
331 char *name, in ti_adpll_init_fixed_factor() argument
338 struct clk *clock; in ti_adpll_init_fixed_factor() local
340 child_name = ti_adpll_clk_get_name(d, -ENODEV, name); in ti_adpll_init_fixed_factor()
342 return -ENOMEM; in ti_adpll_init_fixed_factor()
345 clock = clk_register_fixed_factor(d->dev, child_name, parent_name, in ti_adpll_init_fixed_factor()
347 if (IS_ERR(clock)) in ti_adpll_init_fixed_factor()
348 return PTR_ERR(clock); in ti_adpll_init_fixed_factor()
350 return ti_adpll_setup_clock(d, clock, index, -ENODEV, child_name, in ti_adpll_init_fixed_factor()
359 spin_lock_irqsave(&d->lock, flags); in ti_adpll_set_idle_bypass()
360 v = readl_relaxed(d->regs + ADPLL_CLKCTRL_OFFSET); in ti_adpll_set_idle_bypass()
362 writel_relaxed(v, d->regs + ADPLL_CLKCTRL_OFFSET); in ti_adpll_set_idle_bypass()
363 spin_unlock_irqrestore(&d->lock, flags); in ti_adpll_set_idle_bypass()
371 spin_lock_irqsave(&d->lock, flags); in ti_adpll_clear_idle_bypass()
372 v = readl_relaxed(d->regs + ADPLL_CLKCTRL_OFFSET); in ti_adpll_clear_idle_bypass()
374 writel_relaxed(v, d->regs + ADPLL_CLKCTRL_OFFSET); in ti_adpll_clear_idle_bypass()
375 spin_unlock_irqrestore(&d->lock, flags); in ti_adpll_clear_idle_bypass()
382 v = readl_relaxed(d->regs + ADPLL_STATUS_OFFSET); in ti_adpll_clock_is_bypass()
389 * about the DCO clock and not CLKOUT you can clear M2PWDNZ before enabling
394 u32 v = readl_relaxed(d->regs + ADPLL_STATUS_OFFSET); in ti_adpll_is_locked()
407 } while (retries--); in ti_adpll_wait_lock()
409 dev_err(d->dev, "pll failed to lock\n"); in ti_adpll_wait_lock()
410 return -ETIMEDOUT; in ti_adpll_wait_lock()
441 * Note that the DCO clock is never subject to bypass: if the PLL is off,
456 spin_lock_irqsave(&d->lock, flags); in ti_adpll_recalc_rate()
457 frac_m = readl_relaxed(d->regs + ADPLL_FRACDIV_OFFSET); in ti_adpll_recalc_rate()
459 rate = (u64)readw_relaxed(d->regs + ADPLL_MN2DIV_OFFSET) << 18; in ti_adpll_recalc_rate()
462 divider = (readw_relaxed(d->regs + ADPLL_M2NDIV_OFFSET) + 1) << 18; in ti_adpll_recalc_rate()
463 spin_unlock_irqrestore(&d->lock, flags); in ti_adpll_recalc_rate()
467 if (d->c->is_type_s) { in ti_adpll_recalc_rate()
468 v = readl_relaxed(d->regs + ADPLL_CLKCTRL_OFFSET); in ti_adpll_recalc_rate()
494 struct clk *clock; in ti_adpll_init_dco() local
498 d->outputs.clks = devm_kcalloc(d->dev, in ti_adpll_init_dco()
502 if (!d->outputs.clks) in ti_adpll_init_dco()
503 return -ENOMEM; in ti_adpll_init_dco()
505 if (d->c->output_index < 0) in ti_adpll_init_dco()
510 init.name = ti_adpll_clk_get_name(d, d->c->output_index, postfix); in ti_adpll_init_dco()
511 if (!init.name) in ti_adpll_init_dco()
512 return -EINVAL; in ti_adpll_init_dco()
514 init.parent_names = d->parent_names; in ti_adpll_init_dco()
515 init.num_parents = d->c->nr_max_inputs; in ti_adpll_init_dco()
518 d->dco.hw.init = &init; in ti_adpll_init_dco()
520 if (d->c->is_type_s) in ti_adpll_init_dco()
525 /* Internal input clock divider N2 */ in ti_adpll_init_dco()
526 err = ti_adpll_init_divider(d, TI_ADPLL_N2, -ENODEV, "n2", in ti_adpll_init_dco()
527 d->parent_clocks[TI_ADPLL_CLKINP], in ti_adpll_init_dco()
528 d->regs + ADPLL_MN2DIV_OFFSET, in ti_adpll_init_dco()
533 clock = devm_clk_register(d->dev, &d->dco.hw); in ti_adpll_init_dco()
534 if (IS_ERR(clock)) in ti_adpll_init_dco()
535 return PTR_ERR(clock); in ti_adpll_init_dco()
537 return ti_adpll_setup_clock(d, clock, TI_ADPLL_DCO, d->c->output_index, in ti_adpll_init_dco()
538 init.name, NULL); in ti_adpll_init_dco()
544 struct clk_hw *gate_hw = &co->gate.hw; in ti_adpll_clkout_enable()
554 struct clk_hw *gate_hw = &co->gate.hw; in ti_adpll_clkout_disable()
563 struct clk_hw *gate_hw = &co->gate.hw; in ti_adpll_clkout_is_enabled()
574 struct ti_adpll_data *d = co->adpll; in ti_adpll_clkout_get_parent()
582 char *name, struct clk *clk0, in ti_adpll_init_clkout() argument
590 struct clk *clock; in ti_adpll_init_clkout() local
593 co = devm_kzalloc(d->dev, sizeof(*co), GFP_KERNEL); in ti_adpll_init_clkout()
595 return -ENOMEM; in ti_adpll_init_clkout()
596 co->adpll = d; in ti_adpll_init_clkout()
598 err = of_property_read_string_index(d->np, in ti_adpll_init_clkout()
599 "clock-output-names", in ti_adpll_init_clkout()
605 ops = devm_kzalloc(d->dev, sizeof(*ops), GFP_KERNEL); in ti_adpll_init_clkout()
607 return -ENOMEM; in ti_adpll_init_clkout()
609 init.name = child_name; in ti_adpll_init_clkout()
612 co->hw.init = &init; in ti_adpll_init_clkout()
618 ops->get_parent = ti_adpll_clkout_get_parent; in ti_adpll_init_clkout()
619 ops->determine_rate = __clk_mux_determine_rate; in ti_adpll_init_clkout()
621 co->gate.lock = &d->lock; in ti_adpll_init_clkout()
622 co->gate.reg = d->regs + ADPLL_CLKCTRL_OFFSET; in ti_adpll_init_clkout()
623 co->gate.bit_idx = gate_bit; in ti_adpll_init_clkout()
624 ops->enable = ti_adpll_clkout_enable; in ti_adpll_init_clkout()
625 ops->disable = ti_adpll_clkout_disable; in ti_adpll_init_clkout()
626 ops->is_enabled = ti_adpll_clkout_is_enabled; in ti_adpll_init_clkout()
629 clock = devm_clk_register(d->dev, &co->hw); in ti_adpll_init_clkout()
630 if (IS_ERR(clock)) { in ti_adpll_init_clkout()
631 dev_err(d->dev, "failed to register output %s: %li\n", in ti_adpll_init_clkout()
632 name, PTR_ERR(clock)); in ti_adpll_init_clkout()
633 return PTR_ERR(clock); in ti_adpll_init_clkout()
636 return ti_adpll_setup_clock(d, clock, index, output_index, child_name, in ti_adpll_init_clkout()
644 if (!d->c->is_type_s) in ti_adpll_init_children_adpll_s()
649 d->clocks[TI_ADPLL_N2].clk, in ti_adpll_init_children_adpll_s()
650 d->parent_clocks[TI_ADPLL_CLKINPULOW], in ti_adpll_init_children_adpll_s()
651 d->regs + ADPLL_CLKCTRL_OFFSET, in ti_adpll_init_children_adpll_s()
657 err = ti_adpll_init_divider(d, TI_ADPLL_M2, -ENODEV, "m2", in ti_adpll_init_children_adpll_s()
658 d->clocks[TI_ADPLL_DCO].clk, in ti_adpll_init_children_adpll_s()
659 d->regs + ADPLL_M2NDIV_OFFSET, in ti_adpll_init_children_adpll_s()
668 d->clocks[TI_ADPLL_M2].clk, in ti_adpll_init_children_adpll_s()
676 d->clocks[TI_ADPLL_DIV2].clk, in ti_adpll_init_children_adpll_s()
677 d->clocks[TI_ADPLL_BYPASS].clk); in ti_adpll_init_children_adpll_s()
683 "clkout2", d->clocks[TI_ADPLL_M2].clk, in ti_adpll_init_children_adpll_s()
684 d->clocks[TI_ADPLL_BYPASS].clk); in ti_adpll_init_children_adpll_s()
689 if (d->parent_clocks[TI_ADPLL_CLKINPHIF]) { in ti_adpll_init_children_adpll_s()
691 d->clocks[TI_ADPLL_DCO].clk, in ti_adpll_init_children_adpll_s()
692 d->parent_clocks[TI_ADPLL_CLKINPHIF], in ti_adpll_init_children_adpll_s()
693 d->regs + ADPLL_CLKCTRL_OFFSET, in ti_adpll_init_children_adpll_s()
701 d->clocks[TI_ADPLL_HIF].clk, in ti_adpll_init_children_adpll_s()
702 d->regs + ADPLL_M3DIV_OFFSET, in ti_adpll_init_children_adpll_s()
709 /* Output clock dcoclkldo is the DCO */ in ti_adpll_init_children_adpll_s()
718 if (d->c->is_type_s) in ti_adpll_init_children_adpll_lj()
723 "clkdcoldo", d->clocks[TI_ADPLL_DCO].clk, in ti_adpll_init_children_adpll_lj()
724 d->regs + ADPLL_CLKCTRL_OFFSET, in ti_adpll_init_children_adpll_lj()
730 err = ti_adpll_init_divider(d, TI_ADPLL_M2, -ENODEV, in ti_adpll_init_children_adpll_lj()
731 "m2", d->clocks[TI_ADPLL_DCO].clk, in ti_adpll_init_children_adpll_lj()
732 d->regs + ADPLL_M2NDIV_OFFSET, in ti_adpll_init_children_adpll_lj()
741 "clkoutldo", d->clocks[TI_ADPLL_M2].clk, in ti_adpll_init_children_adpll_lj()
742 d->regs + ADPLL_CLKCTRL_OFFSET, in ti_adpll_init_children_adpll_lj()
750 d->clocks[TI_ADPLL_N2].clk, in ti_adpll_init_children_adpll_lj()
751 d->parent_clocks[TI_ADPLL_CLKINPULOW], in ti_adpll_init_children_adpll_lj()
752 d->regs + ADPLL_CLKCTRL_OFFSET, in ti_adpll_init_children_adpll_lj()
760 d->clocks[TI_ADPLL_M2].clk, in ti_adpll_init_children_adpll_lj()
761 d->clocks[TI_ADPLL_BYPASS].clk); in ti_adpll_init_children_adpll_lj()
772 for (i = TI_ADPLL_M3; i >= 0; i--) { in ti_adpll_free_resources()
773 struct ti_adpll_clock *ac = &d->clocks[i]; in ti_adpll_free_resources()
775 if (!ac || IS_ERR_OR_NULL(ac->clk)) in ti_adpll_free_resources()
777 if (ac->cl) in ti_adpll_free_resources()
778 clkdev_drop(ac->cl); in ti_adpll_free_resources()
779 if (ac->unregister) in ti_adpll_free_resources()
780 ac->unregister(ac->clk); in ti_adpll_free_resources()
798 if (d->c->is_type_s) { in ti_adpll_init_registers()
800 ti_adpll_unlock_all(d->iobase + ADPLL_PLLSS_MMR_LOCK_OFFSET); in ti_adpll_init_registers()
803 d->regs = d->iobase + register_offset + ADPLL_PWRCTRL_OFFSET; in ti_adpll_init_registers()
811 struct clk *clock; in ti_adpll_init_inputs() local
814 nr_inputs = of_clk_get_parent_count(d->np); in ti_adpll_init_inputs()
815 if (nr_inputs < d->c->nr_max_inputs) { in ti_adpll_init_inputs()
816 dev_err(d->dev, error, nr_inputs); in ti_adpll_init_inputs()
817 return -EINVAL; in ti_adpll_init_inputs()
819 of_clk_parent_fill(d->np, d->parent_names, nr_inputs); in ti_adpll_init_inputs()
821 clock = devm_clk_get(d->dev, d->parent_names[0]); in ti_adpll_init_inputs()
822 if (IS_ERR(clock)) { in ti_adpll_init_inputs()
823 dev_err(d->dev, "could not get clkinp\n"); in ti_adpll_init_inputs()
824 return PTR_ERR(clock); in ti_adpll_init_inputs()
826 d->parent_clocks[TI_ADPLL_CLKINP] = clock; in ti_adpll_init_inputs()
828 clock = devm_clk_get(d->dev, d->parent_names[1]); in ti_adpll_init_inputs()
829 if (IS_ERR(clock)) { in ti_adpll_init_inputs()
830 dev_err(d->dev, "could not get clkinpulow clock\n"); in ti_adpll_init_inputs()
831 return PTR_ERR(clock); in ti_adpll_init_inputs()
833 d->parent_clocks[TI_ADPLL_CLKINPULOW] = clock; in ti_adpll_init_inputs()
835 if (d->c->is_type_s) { in ti_adpll_init_inputs()
836 clock = devm_clk_get(d->dev, d->parent_names[2]); in ti_adpll_init_inputs()
837 if (IS_ERR(clock)) { in ti_adpll_init_inputs()
838 dev_err(d->dev, "could not get clkinphif clock\n"); in ti_adpll_init_inputs()
839 return PTR_ERR(clock); in ti_adpll_init_inputs()
841 d->parent_clocks[TI_ADPLL_CLKINPHIF] = clock; in ti_adpll_init_inputs()
856 .nr_max_inputs = MAX_ADPLL_INPUTS - 1,
857 .nr_max_outputs = MAX_ADPLL_OUTPUTS - 1,
858 .output_index = -EINVAL,
862 { .compatible = "ti,dm814-adpll-s-clock", &ti_adpll_type_s },
863 { .compatible = "ti,dm814-adpll-lj-clock", &ti_adpll_type_lj },
870 struct device_node *node = pdev->dev.of_node; in ti_adpll_probe()
871 struct device *dev = &pdev->dev; in ti_adpll_probe()
880 pdata = match->data; in ti_adpll_probe()
882 return -ENODEV; in ti_adpll_probe()
886 return -ENOMEM; in ti_adpll_probe()
887 d->dev = dev; in ti_adpll_probe()
888 d->np = node; in ti_adpll_probe()
889 d->c = pdata; in ti_adpll_probe()
890 dev_set_drvdata(d->dev, d); in ti_adpll_probe()
891 spin_lock_init(&d->lock); in ti_adpll_probe()
895 return -ENODEV; in ti_adpll_probe()
896 d->pa = res->start; in ti_adpll_probe()
898 d->iobase = devm_ioremap_resource(dev, res); in ti_adpll_probe()
899 if (IS_ERR(d->iobase)) { in ti_adpll_probe()
901 PTR_ERR(d->iobase)); in ti_adpll_probe()
902 return PTR_ERR(d->iobase); in ti_adpll_probe()
913 d->clocks = devm_kcalloc(d->dev, in ti_adpll_probe()
917 if (!d->clocks) in ti_adpll_probe()
918 return -ENOMEM; in ti_adpll_probe()
933 err = of_clk_add_provider(d->np, of_clk_src_onecell_get, &d->outputs); in ti_adpll_probe()
948 struct ti_adpll_data *d = dev_get_drvdata(&pdev->dev); in ti_adpll_remove()
957 .name = "ti-adpll",
976 MODULE_DESCRIPTION("Clock driver for dm814x ADPLL");
977 MODULE_ALIAS("platform:dm814-adpll-clock");