Lines Matching full:divider

95  * struct tegra_clk_frac_div - fractional divider clock
98  * @reg:	register containing divider
100  * @shift:	shift to the divider bit field
101  * @width:	width of the divider bit field
106  * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
108  *      flag indicates that this divider is for fixed rate PLL.
110  *      fraction bit is set. This flags indicates to calculate divider for which
112  * TEGRA_DIVIDER_UART - UART module divider has additional enable bit which is
113  *      set when divider value is not 0. This flags indicates that the divider
158  * @n:			feedback divider
159  * @m:			input divider
160  * @p:			post divider
162  * @sdm_data:		fraction divider setting (0 = disabled)
175  * struct pdiv_map - map post divider to hw value
177  * @pdiv:		post divider
188  * @divn_shift:	shift to the feedback divider bit field
189  * @divn_width:	width of the feedback divider bit field
190  * @divm_shift:	shift to the input divider bit field
191  * @divm_width:	width of the input divider bit field
192  * @divp_shift:	shift to the post divider bit field
193  * @divp_width:	width of the post divider bit field
194  * @override_divn_shift: shift to the feedback divider bitfield in override reg
195  * @override_divm_shift: shift to the input divider bitfield in override reg
196  * @override_divp_shift: shift to the post divider bitfield in override reg
233  * @sdm_din_mask:		Mask of SDM divider bits
241  * @pmc_divnm_reg:		n, m divider PMC override register offset (PLLM)
242  * @pmc_divp_reg:		p divider PMC override register offset (PLLM)
247  * @max_p:			maximum value for the p divider
249  * @pdiv_tohw:			mapping of p divider to register values
256  *				PLL's based on fractional divider value.
260  *				divider range (if SDM is present)
283  * TEGRA_PLLU - PLLU has inverted post divider. This flags indicated
284  *     that it is PLLU and invert post divider value.
497  * struct tegra_clk_pll_out - PLL divider down clock
500  * @reg:		register containing the PLL divider
501  * @enb_bit_idx:	bit to enable/disable PLL divider
502  * @rst_bit_idx:	bit to reset PLL divider
614  * @divider:	divider clock
617  * @div_ops:	divider clock ops
624 	struct tegra_clk_frac_div	divider;  member
658 		.divider = {						\
735  * TEGRA_DIVIDER_2 - LP cluster has additional divider. This flag indicates
740  * TEGRA20_SUPER_CLK - Tegra20 doesn't have a dedicated divider for Super
778  * struct tegra_sdmmc_mux - switch divider with Low Jitter inputs for SDMMC
781  * @reg:	register controlling mux and divider