691 	u32 boot_val = readl_relaxed(base + params->ext_misc_reg[misc_num]);  in _pll_misc_chk_default()
745 			clk_base + pllcx->params->ext_misc_reg[0]);  in tegra210_pllcx_set_defaults()
747 			clk_base + pllcx->params->ext_misc_reg[1]);  in tegra210_pllcx_set_defaults()
749 			clk_base + pllcx->params->ext_misc_reg[2]);  in tegra210_pllcx_set_defaults()
751 			clk_base + pllcx->params->ext_misc_reg[3]);  in tegra210_pllcx_set_defaults()
809 		val = readl_relaxed(clk_base + plla->params->ext_misc_reg[0]);  in tegra210_plla_set_defaults()
812 		writel_relaxed(val, clk_base + plla->params->ext_misc_reg[0]);  in tegra210_plla_set_defaults()
822 			clk_base + plla->params->ext_misc_reg[0]);  in tegra210_plla_set_defaults()
824 			clk_base + plla->params->ext_misc_reg[2]);  in tegra210_plla_set_defaults()
862 		val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]);  in tegra210_plld_set_defaults()
865 		writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]);  in tegra210_plld_set_defaults()
871 	val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]);  in tegra210_plld_set_defaults()
875 	writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]);  in tegra210_plld_set_defaults()
877 			plld->params->ext_misc_reg[1]);  in tegra210_plld_set_defaults()
925 		} else if (plldss->params->ext_misc_reg[1]) {  in plldss_defaults()
943 		val = readl_relaxed(clk_base + plldss->params->ext_misc_reg[0]);  in plldss_defaults()
946 		writel_relaxed(val, clk_base + plldss->params->ext_misc_reg[0]);  in plldss_defaults()
958 	if (!plldss->params->ext_misc_reg[1]) {  in plldss_defaults()
960 				plldss->params->ext_misc_reg[0]);  in plldss_defaults()
966 			plldss->params->ext_misc_reg[0]);  in plldss_defaults()
969 			clk_base + plldss->params->ext_misc_reg[1]);  in plldss_defaults()
970 	writel_relaxed(misc2_val, clk_base + plldss->params->ext_misc_reg[2]);  in plldss_defaults()
971 	writel_relaxed(misc3_val, clk_base + plldss->params->ext_misc_reg[3]);  in plldss_defaults()
1033 		val = readl_relaxed(clk_base + pllre->params->ext_misc_reg[0]);  in tegra210_pllre_set_defaults()
1040 		writel_relaxed(val, clk_base + pllre->params->ext_misc_reg[0]);  in tegra210_pllre_set_defaults()
1054 			clk_base + pllre->params->ext_misc_reg[0]);  in tegra210_pllre_set_defaults()
1148 		writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);  in tegra210_pllx_set_defaults()
1151 		val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[0]);  in tegra210_pllx_set_defaults()
1154 		writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[0]);  in tegra210_pllx_set_defaults()
1162 			pllx->params->ext_misc_reg[0]);  in tegra210_pllx_set_defaults()
1166 			pllx->params->ext_misc_reg[1]);  in tegra210_pllx_set_defaults()
1169 	writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);  in tegra210_pllx_set_defaults()
1173 			pllx->params->ext_misc_reg[3]);  in tegra210_pllx_set_defaults()
1177 			pllx->params->ext_misc_reg[4]);  in tegra210_pllx_set_defaults()
1179 			pllx->params->ext_misc_reg[5]);  in tegra210_pllx_set_defaults()
1204 		val = readl_relaxed(clk_base + pllmb->params->ext_misc_reg[0]);  in tegra210_pllmb_set_defaults()
1207 		writel_relaxed(val, clk_base + pllmb->params->ext_misc_reg[0]);  in tegra210_pllmb_set_defaults()
1215 			clk_base + pllmb->params->ext_misc_reg[0]);  in tegra210_pllmb_set_defaults()
1262 		val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[0]);  in tegra210_pllp_set_defaults()
1266 		writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[0]);  in tegra210_pllp_set_defaults()
1274 			clk_base + pllp->params->ext_misc_reg[0]);  in tegra210_pllp_set_defaults()
1277 	val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[1]);  in tegra210_pllp_set_defaults()
1281 	writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[1]);  in tegra210_pllp_set_defaults()
1325 		val = readl_relaxed(clk_base + pllu->ext_misc_reg[0]);  in tegra210_pllu_set_defaults()
1328 		writel_relaxed(val, clk_base + pllu->ext_misc_reg[0]);  in tegra210_pllu_set_defaults()
1330 		val = readl_relaxed(clk_base + pllu->ext_misc_reg[1]);  in tegra210_pllu_set_defaults()
1333 		writel_relaxed(val, clk_base + pllu->ext_misc_reg[1]);  in tegra210_pllu_set_defaults()
1341 			clk_base + pllu->ext_misc_reg[0]);  in tegra210_pllu_set_defaults()
1343 			clk_base + pllu->ext_misc_reg[1]);  in tegra210_pllu_set_defaults()
1387 	val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]);  in tegra210_pllx_dyn_ramp()
1390 	writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);  in tegra210_pllx_dyn_ramp()
1393 	val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]);  in tegra210_pllx_dyn_ramp()
1395 	writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);  in tegra210_pllx_dyn_ramp()
1398 	tegra210_wait_for_mask(pllx, pllx->params->ext_misc_reg[2],  in tegra210_pllx_dyn_ramp()
1408 	writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);  in tegra210_pllx_dyn_ramp()
1614 	.ext_misc_reg[0] = PLLX_MISC0,
1615 	.ext_misc_reg[1] = PLLX_MISC1,
1616 	.ext_misc_reg[2] = PLLX_MISC2,
1617 	.ext_misc_reg[3] = PLLX_MISC3,
1618 	.ext_misc_reg[4] = PLLX_MISC4,
1619 	.ext_misc_reg[5] = PLLX_MISC5,
1669 	.ext_misc_reg[0] = PLLC_MISC0,
1670 	.ext_misc_reg[1] = PLLC_MISC1,
1671 	.ext_misc_reg[2] = PLLC_MISC2,
1672 	.ext_misc_reg[3] = PLLC_MISC3,
1712 	.ext_misc_reg[0] = PLLC2_MISC0,
1713 	.ext_misc_reg[1] = PLLC2_MISC1,
1714 	.ext_misc_reg[2] = PLLC2_MISC2,
1715 	.ext_misc_reg[3] = PLLC2_MISC3,
1742 	.ext_misc_reg[0] = PLLC3_MISC0,
1743 	.ext_misc_reg[1] = PLLC3_MISC1,
1744 	.ext_misc_reg[2] = PLLC3_MISC2,
1745 	.ext_misc_reg[3] = PLLC3_MISC3,
1799 	.ext_misc_reg[0] = PLLC4_MISC0,
1856 	.ext_misc_reg[0] = PLLM_MISC2,
1857 	.ext_misc_reg[1] = PLLM_MISC1,
1882 	.ext_misc_reg[0] = PLLMB_MISC1,
1962 	.ext_misc_reg[0] = PLLRE_MISC0,
2002 	.ext_misc_reg[0] = PLLP_MISC0,
2003 	.ext_misc_reg[1] = PLLP_MISC1,
2030 	.ext_misc_reg[0] = PLLA1_MISC0,
2031 	.ext_misc_reg[1] = PLLA1_MISC1,
2032 	.ext_misc_reg[2] = PLLA1_MISC2,
2033 	.ext_misc_reg[3] = PLLA1_MISC3,
2082 	.ext_misc_reg[0] = PLLA_MISC0,
2083 	.ext_misc_reg[1] = PLLA_MISC1,
2084 	.ext_misc_reg[2] = PLLA_MISC2,
2129 	.ext_misc_reg[0] = PLLD_MISC0,
2130 	.ext_misc_reg[1] = PLLD_MISC1,
2171 	.ext_misc_reg[0] = PLLD2_MISC0,
2172 	.ext_misc_reg[1] = PLLD2_MISC1,
2173 	.ext_misc_reg[2] = PLLD2_MISC2,
2174 	.ext_misc_reg[3] = PLLD2_MISC3,
2214 	.ext_misc_reg[0] = PLLDP_MISC,
2215 	.ext_misc_reg[1] = PLLDP_SS_CFG,
2216 	.ext_misc_reg[2] = PLLDP_SS_CTRL1,
2217 	.ext_misc_reg[3] = PLLDP_SS_CTRL2,
2257 	.ext_misc_reg[0] = PLLU_MISC0,
2258 	.ext_misc_reg[1] = PLLU_MISC1,
2860 	reg = readl_relaxed(clk_base + pllu.params->ext_misc_reg[0]);  in tegra210_enable_pllu()
2862 	writel_relaxed(reg, clk_base + pllu.params->ext_misc_reg[0]);  in tegra210_enable_pllu()