Lines Matching refs:clk_base
298 static void __iomem *clk_base; variable
496 val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0); in tegra210_xusb_pll_hw_control_enable()
501 writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0); in tegra210_xusb_pll_hw_control_enable()
509 val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0); in tegra210_xusb_pll_hw_sequence_start()
511 writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0); in tegra210_xusb_pll_hw_sequence_start()
519 val = readl_relaxed(clk_base + SATA_PLL_CFG0); in tegra210_sata_pll_hw_control_enable()
523 writel_relaxed(val, clk_base + SATA_PLL_CFG0); in tegra210_sata_pll_hw_control_enable()
531 val = readl_relaxed(clk_base + SATA_PLL_CFG0); in tegra210_sata_pll_hw_sequence_start()
533 writel_relaxed(val, clk_base + SATA_PLL_CFG0); in tegra210_sata_pll_hw_sequence_start()
541 val = readl_relaxed(clk_base + SATA_PLL_CFG0); in tegra210_set_sata_pll_seq_sw()
553 writel_relaxed(val, clk_base + SATA_PLL_CFG0); in tegra210_set_sata_pll_seq_sw()
562 writel_relaxed(CLK_OUT_ENB_X_CLK_ENB_EMC_DLL, clk_base + offset); in tegra210_clk_emc_dll_enable()
568 writel_relaxed(emc_dll_src_value, clk_base + CLK_SOURCE_EMC_DLL); in tegra210_clk_emc_dll_update_setting()
574 writel_relaxed(emc_src_value, clk_base + CLK_SOURCE_EMC); in tegra210_clk_emc_update_setting()
582 val = readl_relaxed(clk_base + mbist->lvl2_offset); in tegra210_generic_mbist_war()
583 writel_relaxed(val | mbist->lvl2_mask, clk_base + mbist->lvl2_offset); in tegra210_generic_mbist_war()
584 fence_udelay(1, clk_base); in tegra210_generic_mbist_war()
585 writel_relaxed(val, clk_base + mbist->lvl2_offset); in tegra210_generic_mbist_war()
586 fence_udelay(1, clk_base); in tegra210_generic_mbist_war()
596 csi_src = readl_relaxed(clk_base + PLLD_BASE); in tegra210_venc_mbist_war()
597 writel_relaxed(csi_src | PLLD_BASE_CSI_CLKSOURCE, clk_base + PLLD_BASE); in tegra210_venc_mbist_war()
598 fence_udelay(1, clk_base); in tegra210_venc_mbist_war()
600 ovra = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRA); in tegra210_venc_mbist_war()
601 writel_relaxed(ovra | BIT(15), clk_base + LVL2_CLK_GATE_OVRA); in tegra210_venc_mbist_war()
602 ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE); in tegra210_venc_mbist_war()
603 writel_relaxed(ovre | BIT(3), clk_base + LVL2_CLK_GATE_OVRE); in tegra210_venc_mbist_war()
604 fence_udelay(1, clk_base); in tegra210_venc_mbist_war()
606 writel_relaxed(ovra, clk_base + LVL2_CLK_GATE_OVRA); in tegra210_venc_mbist_war()
607 writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE); in tegra210_venc_mbist_war()
608 writel_relaxed(csi_src, clk_base + PLLD_BASE); in tegra210_venc_mbist_war()
609 fence_udelay(1, clk_base); in tegra210_venc_mbist_war()
618 ovra = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRA); in tegra210_disp_mbist_war()
619 writel_relaxed(ovra | BIT(1), clk_base + LVL2_CLK_GATE_OVRA); in tegra210_disp_mbist_war()
620 fence_udelay(1, clk_base); in tegra210_disp_mbist_war()
628 writel_relaxed(ovra, clk_base + LVL2_CLK_GATE_OVRA); in tegra210_disp_mbist_war()
629 fence_udelay(1, clk_base); in tegra210_disp_mbist_war()
636 ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE); in tegra210_vic_mbist_war()
637 writel_relaxed(ovre | BIT(5), clk_base + LVL2_CLK_GATE_OVRE); in tegra210_vic_mbist_war()
638 fence_udelay(1, clk_base); in tegra210_vic_mbist_war()
648 writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE); in tegra210_vic_mbist_war()
649 fence_udelay(1, clk_base); in tegra210_vic_mbist_war()
658 ovrc = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRC); in tegra210_ape_mbist_war()
659 ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE); in tegra210_ape_mbist_war()
660 writel_relaxed(ovrc | BIT(1), clk_base + LVL2_CLK_GATE_OVRC); in tegra210_ape_mbist_war()
662 clk_base + LVL2_CLK_GATE_OVRE); in tegra210_ape_mbist_war()
663 fence_udelay(1, clk_base); in tegra210_ape_mbist_war()
682 writel_relaxed(ovrc, clk_base + LVL2_CLK_GATE_OVRC); in tegra210_ape_mbist_war()
683 writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE); in tegra210_ape_mbist_war()
684 fence_udelay(1, clk_base); in tegra210_ape_mbist_war()
713 _pll_misc_chk_default(clk_base, params, 0, default_val, in pllcx_check_defaults()
717 _pll_misc_chk_default(clk_base, params, 1, default_val, in pllcx_check_defaults()
721 _pll_misc_chk_default(clk_base, params, 2, default_val, in pllcx_check_defaults()
725 _pll_misc_chk_default(clk_base, params, 3, default_val, in pllcx_check_defaults()
734 if (readl_relaxed(clk_base + pllcx->params->base_reg) & PLL_ENABLE) { in tegra210_pllcx_set_defaults()
745 clk_base + pllcx->params->ext_misc_reg[0]); in tegra210_pllcx_set_defaults()
747 clk_base + pllcx->params->ext_misc_reg[1]); in tegra210_pllcx_set_defaults()
749 clk_base + pllcx->params->ext_misc_reg[2]); in tegra210_pllcx_set_defaults()
751 clk_base + pllcx->params->ext_misc_reg[3]); in tegra210_pllcx_set_defaults()
783 u32 val = readl_relaxed(clk_base + plla->params->base_reg); in tegra210_plla_set_defaults()
801 _pll_misc_chk_default(clk_base, plla->params, 0, val, in tegra210_plla_set_defaults()
805 _pll_misc_chk_default(clk_base, plla->params, 2, val, in tegra210_plla_set_defaults()
809 val = readl_relaxed(clk_base + plla->params->ext_misc_reg[0]); in tegra210_plla_set_defaults()
812 writel_relaxed(val, clk_base + plla->params->ext_misc_reg[0]); in tegra210_plla_set_defaults()
820 writel_relaxed(val, clk_base + plla->params->base_reg); in tegra210_plla_set_defaults()
822 clk_base + plla->params->ext_misc_reg[0]); in tegra210_plla_set_defaults()
824 clk_base + plla->params->ext_misc_reg[2]); in tegra210_plla_set_defaults()
839 if (readl_relaxed(clk_base + plld->params->base_reg) & in tegra210_plld_set_defaults()
847 _pll_misc_chk_default(clk_base, plld->params, 1, in tegra210_plld_set_defaults()
854 _pll_misc_chk_default(clk_base, plld->params, 0, val, in tegra210_plld_set_defaults()
862 val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]); in tegra210_plld_set_defaults()
865 writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]); in tegra210_plld_set_defaults()
871 val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]); in tegra210_plld_set_defaults()
875 writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]); in tegra210_plld_set_defaults()
876 writel_relaxed(PLLD_MISC1_DEFAULT_VALUE, clk_base + in tegra210_plld_set_defaults()
889 u32 val = readl_relaxed(clk_base + plldss->params->base_reg); in plldss_defaults()
906 _pll_misc_chk_default(clk_base, plldss->params, 0, default_val, in plldss_defaults()
917 _pll_misc_chk_default(clk_base, plldss->params, 1, in plldss_defaults()
920 _pll_misc_chk_default(clk_base, plldss->params, 2, in plldss_defaults()
923 _pll_misc_chk_default(clk_base, plldss->params, 3, in plldss_defaults()
927 _pll_misc_chk_default(clk_base, plldss->params, 1, in plldss_defaults()
939 writel_relaxed(val, clk_base + in plldss_defaults()
943 val = readl_relaxed(clk_base + plldss->params->ext_misc_reg[0]); in plldss_defaults()
946 writel_relaxed(val, clk_base + plldss->params->ext_misc_reg[0]); in plldss_defaults()
955 writel_relaxed(val, clk_base + plldss->params->base_reg); in plldss_defaults()
959 writel_relaxed(misc0_val, clk_base + in plldss_defaults()
965 writel_relaxed(misc0_val, clk_base + in plldss_defaults()
969 clk_base + plldss->params->ext_misc_reg[1]); in plldss_defaults()
970 writel_relaxed(misc2_val, clk_base + plldss->params->ext_misc_reg[2]); in plldss_defaults()
971 writel_relaxed(misc3_val, clk_base + plldss->params->ext_misc_reg[3]); in plldss_defaults()
1008 u32 val = readl_relaxed(clk_base + pllre->params->base_reg); in tegra210_pllre_set_defaults()
1029 _pll_misc_chk_default(clk_base, pllre->params, 0, val, in tegra210_pllre_set_defaults()
1033 val = readl_relaxed(clk_base + pllre->params->ext_misc_reg[0]); in tegra210_pllre_set_defaults()
1040 writel_relaxed(val, clk_base + pllre->params->ext_misc_reg[0]); in tegra210_pllre_set_defaults()
1052 writel_relaxed(val, clk_base + pllre->params->base_reg); in tegra210_pllre_set_defaults()
1054 clk_base + pllre->params->ext_misc_reg[0]); in tegra210_pllre_set_defaults()
1098 _pll_misc_chk_default(clk_base, pll->params, 0, default_val, in pllx_check_defaults()
1102 _pll_misc_chk_default(clk_base, pll->params, 1, default_val, in pllx_check_defaults()
1107 _pll_misc_chk_default(clk_base, pll->params, 2, in pllx_check_defaults()
1111 _pll_misc_chk_default(clk_base, pll->params, 3, default_val, in pllx_check_defaults()
1115 _pll_misc_chk_default(clk_base, pll->params, 4, default_val, in pllx_check_defaults()
1119 _pll_misc_chk_default(clk_base, pll->params, 5, default_val, in pllx_check_defaults()
1137 if (readl_relaxed(clk_base + pllx->params->base_reg) & PLL_ENABLE) { in tegra210_pllx_set_defaults()
1148 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); in tegra210_pllx_set_defaults()
1151 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[0]); in tegra210_pllx_set_defaults()
1154 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[0]); in tegra210_pllx_set_defaults()
1161 writel_relaxed(PLLX_MISC0_DEFAULT_VALUE, clk_base + in tegra210_pllx_set_defaults()
1165 writel_relaxed(PLLX_MISC1_DEFAULT_VALUE, clk_base + in tegra210_pllx_set_defaults()
1169 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); in tegra210_pllx_set_defaults()
1172 writel_relaxed(PLLX_MISC3_DEFAULT_VALUE, clk_base + in tegra210_pllx_set_defaults()
1176 writel_relaxed(PLLX_MISC4_DEFAULT_VALUE, clk_base + in tegra210_pllx_set_defaults()
1178 writel_relaxed(PLLX_MISC5_DEFAULT_VALUE, clk_base + in tegra210_pllx_set_defaults()
1186 u32 mask, val = readl_relaxed(clk_base + pllmb->params->base_reg); in tegra210_pllmb_set_defaults()
1198 _pll_misc_chk_default(clk_base, pllmb->params, 0, val, in tegra210_pllmb_set_defaults()
1204 val = readl_relaxed(clk_base + pllmb->params->ext_misc_reg[0]); in tegra210_pllmb_set_defaults()
1207 writel_relaxed(val, clk_base + pllmb->params->ext_misc_reg[0]); in tegra210_pllmb_set_defaults()
1215 clk_base + pllmb->params->ext_misc_reg[0]); in tegra210_pllmb_set_defaults()
1234 _pll_misc_chk_default(clk_base, pll->params, 0, val, in pllp_check_defaults()
1240 _pll_misc_chk_default(clk_base, pll->params, 1, val, in pllp_check_defaults()
1247 u32 val = readl_relaxed(clk_base + pllp->params->base_reg); in tegra210_pllp_set_defaults()
1262 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[0]); in tegra210_pllp_set_defaults()
1266 writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[0]); in tegra210_pllp_set_defaults()
1274 clk_base + pllp->params->ext_misc_reg[0]); in tegra210_pllp_set_defaults()
1277 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[1]); in tegra210_pllp_set_defaults()
1281 writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[1]); in tegra210_pllp_set_defaults()
1299 _pll_misc_chk_default(clk_base, params, 0, val, in pllu_check_defaults()
1304 _pll_misc_chk_default(clk_base, params, 1, val, in pllu_check_defaults()
1310 u32 val = readl_relaxed(clk_base + pllu->base_reg); in tegra210_pllu_set_defaults()
1325 val = readl_relaxed(clk_base + pllu->ext_misc_reg[0]); in tegra210_pllu_set_defaults()
1328 writel_relaxed(val, clk_base + pllu->ext_misc_reg[0]); in tegra210_pllu_set_defaults()
1330 val = readl_relaxed(clk_base + pllu->ext_misc_reg[1]); in tegra210_pllu_set_defaults()
1333 writel_relaxed(val, clk_base + pllu->ext_misc_reg[1]); in tegra210_pllu_set_defaults()
1341 clk_base + pllu->ext_misc_reg[0]); in tegra210_pllu_set_defaults()
1343 clk_base + pllu->ext_misc_reg[1]); in tegra210_pllu_set_defaults()
1370 val = readl_relaxed(clk_base + reg); in tegra210_wait_for_mask()
1387 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]); in tegra210_pllx_dyn_ramp()
1390 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); in tegra210_pllx_dyn_ramp()
1393 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]); in tegra210_pllx_dyn_ramp()
1395 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); in tegra210_pllx_dyn_ramp()
1401 base = readl_relaxed(clk_base + pllx->params->base_reg) & in tegra210_pllx_dyn_ramp()
1404 writel_relaxed(base, clk_base + pllx->params->base_reg); in tegra210_pllx_dyn_ramp()
1408 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); in tegra210_pllx_dyn_ramp()
2728 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_put_utmipll_in_iddq()
2736 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_put_utmipll_in_iddq()
2744 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_put_utmipll_out_iddq()
2746 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_put_utmipll_out_iddq()
2766 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_utmi_param_configure()
2768 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_utmi_param_configure()
2772 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2); in tegra210_utmi_param_configure()
2782 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2); in tegra210_utmi_param_configure()
2785 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); in tegra210_utmi_param_configure()
2796 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); in tegra210_utmi_param_configure()
2799 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); in tegra210_utmi_param_configure()
2802 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); in tegra210_utmi_param_configure()
2807 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2); in tegra210_utmi_param_configure()
2814 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2); in tegra210_utmi_param_configure()
2817 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); in tegra210_utmi_param_configure()
2820 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); in tegra210_utmi_param_configure()
2822 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_utmi_param_configure()
2825 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_utmi_param_configure()
2829 reg = readl_relaxed(clk_base + XUSB_PLL_CFG0); in tegra210_utmi_param_configure()
2831 writel_relaxed(reg, clk_base + XUSB_PLL_CFG0); in tegra210_utmi_param_configure()
2836 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_utmi_param_configure()
2838 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_utmi_param_configure()
2860 reg = readl_relaxed(clk_base + pllu.params->ext_misc_reg[0]); in tegra210_enable_pllu()
2862 writel_relaxed(reg, clk_base + pllu.params->ext_misc_reg[0]); in tegra210_enable_pllu()
2863 fence_udelay(5, clk_base); in tegra210_enable_pllu()
2865 reg = readl_relaxed(clk_base + PLLU_BASE); in tegra210_enable_pllu()
2870 writel(reg, clk_base + PLLU_BASE); in tegra210_enable_pllu()
2871 fence_udelay(1, clk_base); in tegra210_enable_pllu()
2873 writel(reg, clk_base + PLLU_BASE); in tegra210_enable_pllu()
2897 reg = readl_relaxed(clk_base + PLLU_BASE); in tegra210_init_pllu()
2907 reg = readl_relaxed(clk_base + PLLU_BASE); in tegra210_init_pllu()
2909 writel(reg, clk_base + PLLU_BASE); in tegra210_init_pllu()
2911 reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0); in tegra210_init_pllu()
2917 writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0); in tegra210_init_pllu()
2919 reg = readl_relaxed(clk_base + XUSB_PLL_CFG0); in tegra210_init_pllu()
2921 writel_relaxed(reg, clk_base + XUSB_PLL_CFG0); in tegra210_init_pllu()
2922 fence_udelay(1, clk_base); in tegra210_init_pllu()
2924 reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0); in tegra210_init_pllu()
2926 writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0); in tegra210_init_pllu()
2927 fence_udelay(1, clk_base); in tegra210_init_pllu()
2929 reg = readl_relaxed(clk_base + PLLU_BASE); in tegra210_init_pllu()
2931 writel_relaxed(reg, clk_base + PLLU_BASE); in tegra210_init_pllu()
2935 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_init_pllu()
2990 clk_base + CLK_SOURCE_EMC, in tegra210_clk_register_mc()
3039 void __iomem *clk_base, in tegra210_periph_clk_init() argument
3050 clk = tegra_clk_register_periph_fixed("sor_safe", "pll_p", 0, clk_base, in tegra210_periph_clk_init()
3054 clk = tegra_clk_register_periph_fixed("dpaux", "sor_safe", 0, clk_base, in tegra210_periph_clk_init()
3058 clk = tegra_clk_register_periph_fixed("dpaux1", "sor_safe", 0, clk_base, in tegra210_periph_clk_init()
3064 clk_base + PLLD_MISC0, 21, 0, &pll_d_lock); in tegra210_periph_clk_init()
3069 clk_base, 0, 48, in tegra210_periph_clk_init()
3075 clk_base, 0, 82, in tegra210_periph_clk_init()
3081 CLK_SET_RATE_PARENT, clk_base + PLLD_BASE, in tegra210_periph_clk_init()
3088 ARRAY_SIZE(la_parents), &tegra210_la, clk_base, in tegra210_periph_clk_init()
3093 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX, in tegra210_periph_clk_init()
3099 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX, in tegra210_periph_clk_init()
3105 ARRAY_SIZE(aclk_parents), 0, clk_base + 0x6e0, in tegra210_periph_clk_init()
3109 clk = tegra_clk_register_sdmmc_mux_div("sdmmc2", clk_base, in tegra210_periph_clk_init()
3114 clk = tegra_clk_register_sdmmc_mux_div("sdmmc4", clk_base, in tegra210_periph_clk_init()
3129 clk = tegra_clk_register_periph_data(clk_base, init); in tegra210_periph_clk_init()
3133 tegra_periph_clk_init(clk_base, pmc_base, tegra210_clks, &pll_p_params); in tegra210_periph_clk_init()
3136 clk = tegra210_clk_register_emc(np, clk_base); in tegra210_periph_clk_init()
3143 static void __init tegra210_pll_init(void __iomem *clk_base, in tegra210_pll_init() argument
3149 clk = tegra_clk_register_pllc_tegra210("pll_c", "pll_ref", clk_base, in tegra210_pll_init()
3157 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra210_pll_init()
3160 clk_base + PLLC_OUT, 1, 0, in tegra210_pll_init()
3172 clk = tegra_clk_register_pllc_tegra210("pll_c2", "pll_ref", clk_base, in tegra210_pll_init()
3178 clk = tegra_clk_register_pllc_tegra210("pll_c3", "pll_ref", clk_base, in tegra210_pll_init()
3184 clk = tegra_clk_register_pllm("pll_m", "osc", clk_base, pmc, in tegra210_pll_init()
3190 clk = tegra_clk_register_pllmb("pll_mb", "osc", clk_base, pmc, in tegra210_pll_init()
3222 clk_base + PLLU_BASE, 16, 4, 0, in tegra210_pll_init()
3229 clk_base + PLLU_OUTA, 0, in tegra210_pll_init()
3233 clk_base + PLLU_OUTA, 1, 0, in tegra210_pll_init()
3240 clk_base + PLLU_OUTA, 0, in tegra210_pll_init()
3244 clk_base + PLLU_OUTA, 17, 16, in tegra210_pll_init()
3251 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, in tegra210_pll_init()
3258 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, in tegra210_pll_init()
3265 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, in tegra210_pll_init()
3271 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0, in tegra210_pll_init()
3284 clk_base, pmc, 0, in tegra210_pll_init()
3291 clk_base + PLLRE_BASE, 16, 5, 0, in tegra210_pll_init()
3297 clk_base + PLLRE_OUT1, 0, in tegra210_pll_init()
3301 clk_base + PLLRE_OUT1, 1, 0, in tegra210_pll_init()
3307 clk_base, 0, &pll_e_params, NULL); in tegra210_pll_init()
3312 clk = tegra_clk_register_pllre("pll_c4_vco", "pll_ref", clk_base, pmc, in tegra210_pll_init()
3319 clk_base + PLLC4_BASE, 19, 4, 0, in tegra210_pll_init()
3338 clk_base + PLLC4_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra210_pll_init()
3341 clk_base + PLLC4_OUT, 1, 0, in tegra210_pll_init()
3347 clk = tegra_clk_register_pllss_tegra210("pll_dp", "pll_ref", clk_base, in tegra210_pll_init()
3353 clk = tegra_clk_register_pllss_tegra210("pll_d2", "pll_ref", clk_base, in tegra210_pll_init()
3378 reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS); in tegra210_wait_cpu_in_reset()
3389 #define car_readl(_base, _off) readl_relaxed(clk_base + (_base) + ((_off) * 4))
3391 writel_relaxed(_val, clk_base + (_base) + ((_off) * 4))
3406 spare_reg_ctx = readl_relaxed(clk_base + SPARE_REG0); in tegra210_clk_suspend()
3407 misc_clk_enb_ctx = readl_relaxed(clk_base + MISC_CLK_ENB); in tegra210_clk_suspend()
3408 clk_msk_arm_ctx = readl_relaxed(clk_base + CLK_MASK_ARM); in tegra210_clk_suspend()
3421 tegra_clk_osc_resume(clk_base); in tegra210_clk_resume()
3427 writel_relaxed(spare_reg_ctx, clk_base + SPARE_REG0); in tegra210_clk_resume()
3428 writel_relaxed(misc_clk_enb_ctx, clk_base + MISC_CLK_ENB); in tegra210_clk_resume()
3429 writel_relaxed(clk_msk_arm_ctx, clk_base + CLK_MASK_ARM); in tegra210_clk_resume()
3441 writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_L, clk_base + CLK_OUT_ENB_L); in tegra210_clk_resume()
3442 writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_H, clk_base + CLK_OUT_ENB_H); in tegra210_clk_resume()
3443 writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_U, clk_base + CLK_OUT_ENB_U); in tegra210_clk_resume()
3444 writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_V, clk_base + CLK_OUT_ENB_V); in tegra210_clk_resume()
3445 writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_W, clk_base + CLK_OUT_ENB_W); in tegra210_clk_resume()
3446 writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_X, clk_base + CLK_OUT_ENB_X); in tegra210_clk_resume()
3447 writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_Y, clk_base + CLK_OUT_ENB_Y); in tegra210_clk_resume()
3450 fence_udelay(2, clk_base); in tegra210_clk_resume()
3464 readl(clk_base + CLK_SOURCE_CSITE); in tegra210_cpu_clock_suspend()
3465 writel(3 << 30, clk_base + CLK_SOURCE_CSITE); in tegra210_cpu_clock_suspend()
3471 clk_base + CLK_SOURCE_CSITE); in tegra210_cpu_clock_resume()
3574 readl_relaxed(clk_base + RST_DFLL_DVCO); in tegra210_car_barrier()
3586 v = readl_relaxed(clk_base + RST_DFLL_DVCO); in tegra210_clock_assert_dfll_dvco_reset()
3588 writel_relaxed(v, clk_base + RST_DFLL_DVCO); in tegra210_clock_assert_dfll_dvco_reset()
3602 v = readl_relaxed(clk_base + RST_DFLL_DVCO); in tegra210_clock_deassert_dfll_dvco_reset()
3604 writel_relaxed(v, clk_base + RST_DFLL_DVCO); in tegra210_clock_deassert_dfll_dvco_reset()
3614 clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_SET); in tegra210_reset_assert()
3626 writel(BIT(21), clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_CLR); in tegra210_reset_deassert()
3634 clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_CLR); in tegra210_reset_deassert()
3686 clk_base = of_iomap(np, 0); in tegra210_clock_init()
3687 if (!clk_base) { in tegra210_clock_init()
3724 clks = tegra_clk_init(clk_base, TEGRA210_CLK_CLK_MAX, in tegra210_clock_init()
3729 value = readl(clk_base + SPARE_REG0) >> CLK_M_DIVISOR_SHIFT; in tegra210_clock_init()
3732 if (tegra_osc_clk_init(clk_base, tegra210_clks, tegra210_input_freq, in tegra210_clock_init()
3738 tegra210_pll_init(clk_base, pmc_base); in tegra210_clock_init()
3739 tegra210_periph_clk_init(np, clk_base, pmc_base); in tegra210_clock_init()
3740 tegra_audio_clk_init(clk_base, pmc_base, tegra210_clks, in tegra210_clock_init()
3745 value = readl(clk_base + PLLD_BASE); in tegra210_clock_init()
3747 writel(value, clk_base + PLLD_BASE); in tegra210_clock_init()
3751 tegra_super_clk_gen5_init(clk_base, pmc_base, tegra210_clks, in tegra210_clock_init()