Lines Matching refs:UTMIPLL_HW_PWRDN_CFG0
197 #define UTMIPLL_HW_PWRDN_CFG0 0x52c macro
2728 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_put_utmipll_in_iddq()
2736 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_put_utmipll_in_iddq()
2744 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_put_utmipll_out_iddq()
2746 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_put_utmipll_out_iddq()
2766 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_utmi_param_configure()
2768 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_utmi_param_configure()
2822 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_utmi_param_configure()
2825 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_utmi_param_configure()
2836 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_utmi_param_configure()
2838 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_utmi_param_configure()
2935 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_init_pllu()