133 			    _clk_num, _gate_flags, _clk_id)	\  argument
136 			_clk_num,  _gate_flags, _clk_id, _parents##_idx, 0,\
140 			    _clk_num, _gate_flags, _clk_id, flags)\  argument
143 			_clk_num, _gate_flags, _clk_id, _parents##_idx, flags,\
147 			     _clk_num, _gate_flags, _clk_id)	\  argument
150 			_clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\
153 #define MUX8_NOGATE_LOCK(_name, _parents, _offset, _clk_id, _lock)	\  argument
156 			      0, TEGRA_PERIPH_NO_GATE, _clk_id,\
159 #define MUX8_NOGATE(_name, _parents, _offset, _clk_id)	\  argument
162 			      0, TEGRA_PERIPH_NO_GATE, _clk_id,\
166 			    _clk_num, _gate_flags, _clk_id)	\  argument
170 			_clk_id, _parents##_idx, 0, NULL)
173 			    _clk_num, _gate_flags, _clk_id, flags)\  argument
177 			_clk_id, _parents##_idx, flags, NULL)
180 			    _clk_num, _gate_flags, _clk_id)	\  argument
184 			_clk_id, _parents##_idx, 0, NULL)
187 			     _clk_num, _clk_id)			\  argument
190 			TEGRA_DIVIDER_ROUND_UP, _clk_num, 0, _clk_id,\
194 			     _clk_num, _clk_id)			\  argument
197 			TEGRA_DIVIDER_ROUND_UP, _clk_num, 0, _clk_id,\
201 			     _clk_num, _clk_id)			\  argument
204 			_clk_num, TEGRA_PERIPH_ON_APB, _clk_id, \
208 			     _clk_num, _gate_flags, _clk_id)	 \  argument
212 			_clk_id, _parents##_idx, 0, NULL)
215 				 _gate_flags, _clk_id)		\  argument
219 			_clk_id, mux_d_audio_clk_idx, 0, NULL)
223 			      _gate_flags, _clk_id, _lock)		\  argument
227 			_clk_id, _parents##_idx, 0, _lock)
230 			     _clk_num, _gate_flags,  _clk_id, _flags)	\  argument
233 		.clk_id = _clk_id,					\
240 #define DIV8(_name, _parent_name, _offset, _clk_id, _flags)		\  argument
243 		.clk_id = _clk_id,					\