Lines Matching refs:pll_params
1198 static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params, in _pll_fixed_mdiv() argument
1201 u16 mdiv = parent_rate / pll_params->cf_min; in _pll_fixed_mdiv()
1203 if (pll_params->flags & TEGRA_MDIV_NEW) in _pll_fixed_mdiv()
1204 return (!pll_params->mdiv_default ? mdiv : in _pll_fixed_mdiv()
1205 min(mdiv, pll_params->mdiv_default)); in _pll_fixed_mdiv()
1207 if (pll_params->mdiv_default) in _pll_fixed_mdiv()
1208 return pll_params->mdiv_default; in _pll_fixed_mdiv()
1210 if (parent_rate > pll_params->cf_max) in _pll_fixed_mdiv()
1263 static int _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params, in _setup_dynamic_ramp() argument
1292 val = step_a << pll_params->stepa_shift; in _setup_dynamic_ramp()
1293 val |= step_b << pll_params->stepb_shift; in _setup_dynamic_ramp()
1294 writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg); in _setup_dynamic_ramp()
1868 void __iomem *pmc, struct tegra_clk_pll_params *pll_params, in _tegra_init_pll() argument
1880 pll->params = pll_params; in _tegra_init_pll()
1883 if (!pll_params->div_nmp) in _tegra_init_pll()
1884 pll_params->div_nmp = &default_nmp; in _tegra_init_pll()
1920 unsigned long flags, struct tegra_clk_pll_params *pll_params, in tegra_clk_register_pll() argument
1926 pll_params->flags |= TEGRA_PLL_BYPASS; in tegra_clk_register_pll()
1928 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_pll()
1951 unsigned long flags, struct tegra_clk_pll_params *pll_params, in tegra_clk_register_plle() argument
1957 pll_params->flags |= TEGRA_PLL_BYPASS; in tegra_clk_register_plle()
1959 if (!pll_params->div_nmp) in tegra_clk_register_plle()
1960 pll_params->div_nmp = &pll_e_nmp; in tegra_clk_register_plle()
1962 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_plle()
1976 struct tegra_clk_pll_params *pll_params, spinlock_t *lock) in tegra_clk_register_pllu() argument
1981 pll_params->flags |= TEGRA_PLLU; in tegra_clk_register_pllu()
1983 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); in tegra_clk_register_pllu()
2043 struct tegra_clk_pll_params *pll_params, in tegra_clk_register_pllxc() argument
2058 if (!pll_params->pdiv_tohw) in tegra_clk_register_pllxc()
2063 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllxc()
2065 if (pll_params->adjust_vco) in tegra_clk_register_pllxc()
2066 pll_params->vco_min = pll_params->adjust_vco(pll_params, in tegra_clk_register_pllxc()
2073 if (!pll_params->set_defaults) { in tegra_clk_register_pllxc()
2076 err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate); in tegra_clk_register_pllxc()
2080 val = readl_relaxed(clk_base + pll_params->base_reg); in tegra_clk_register_pllxc()
2081 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg); in tegra_clk_register_pllxc()
2084 WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx)); in tegra_clk_register_pllxc()
2086 val_iddq |= BIT(pll_params->iddq_bit_idx); in tegra_clk_register_pllxc()
2088 clk_base + pll_params->iddq_reg); in tegra_clk_register_pllxc()
2092 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_pllxc()
2107 struct tegra_clk_pll_params *pll_params, in tegra_clk_register_pllre() argument
2114 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllre()
2116 if (pll_params->adjust_vco) in tegra_clk_register_pllre()
2117 pll_params->vco_min = pll_params->adjust_vco(pll_params, in tegra_clk_register_pllre()
2120 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_pllre()
2128 WARN_ON(readl_relaxed(clk_base + pll_params->iddq_reg) & in tegra_clk_register_pllre()
2129 BIT(pll_params->iddq_bit_idx)); in tegra_clk_register_pllre()
2133 m = _pll_fixed_mdiv(pll_params, parent_rate); in tegra_clk_register_pllre()
2135 val |= (pll_params->vco_min / parent_rate) << divn_shift(pll); in tegra_clk_register_pllre()
2156 struct tegra_clk_pll_params *pll_params, in tegra_clk_register_pllm() argument
2163 if (!pll_params->pdiv_tohw) in tegra_clk_register_pllm()
2175 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllm()
2177 if (pll_params->adjust_vco) in tegra_clk_register_pllm()
2178 pll_params->vco_min = pll_params->adjust_vco(pll_params, in tegra_clk_register_pllm()
2181 pll_params->flags |= TEGRA_PLL_BYPASS; in tegra_clk_register_pllm()
2182 pll_params->flags |= TEGRA_PLLM; in tegra_clk_register_pllm()
2183 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_pllm()
2198 struct tegra_clk_pll_params *pll_params, in tegra_clk_register_pllc() argument
2202 const struct pdiv_map *p_tohw = pll_params->pdiv_tohw; in tegra_clk_register_pllc()
2219 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllc()
2221 pll_params->flags |= TEGRA_PLL_BYPASS; in tegra_clk_register_pllc()
2222 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_pllc()
2235 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate); in tegra_clk_register_pllc()
2236 cfg.n = cfg.m * pll_params->vco_min / parent_rate; in tegra_clk_register_pllc()
2255 pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll); in tegra_clk_register_pllc()
2256 pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll); in tegra_clk_register_pllc()
2257 pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll); in tegra_clk_register_pllc()
2272 struct tegra_clk_pll_params *pll_params, in tegra_clk_register_plle_tegra114() argument
2278 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); in tegra_clk_register_plle_tegra114()
2295 struct tegra_clk_pll_params *pll_params, in tegra_clk_register_pllu_tegra114() argument
2301 pll_params->flags |= TEGRA_PLLU; in tegra_clk_register_pllu_tegra114()
2303 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); in tegra_clk_register_pllu_tegra114()
2329 struct tegra_clk_pll_params *pll_params, in tegra_clk_register_pllss() argument
2339 if (!pll_params->div_nmp) in tegra_clk_register_pllss()
2349 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); in tegra_clk_register_pllss()
2359 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllss()
2363 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate); in tegra_clk_register_pllss()
2364 cfg.n = cfg.m * pll_params->vco_min / parent_rate; in tegra_clk_register_pllss()
2366 for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++) in tegra_clk_register_pllss()
2373 cfg.p = pll_params->pdiv_tohw[i-1].hw_val; in tegra_clk_register_pllss()
2378 pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll); in tegra_clk_register_pllss()
2379 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll); in tegra_clk_register_pllss()
2380 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll); in tegra_clk_register_pllss()
2383 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg); in tegra_clk_register_pllss()
2385 if (val_iddq & BIT(pll_params->iddq_bit_idx)) { in tegra_clk_register_pllss()
2391 val_iddq |= BIT(pll_params->iddq_bit_idx); in tegra_clk_register_pllss()
2392 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg); in tegra_clk_register_pllss()
2412 struct tegra_clk_pll_params *pll_params, in tegra_clk_register_pllre_tegra210() argument
2418 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllre_tegra210()
2420 if (pll_params->adjust_vco) in tegra_clk_register_pllre_tegra210()
2421 pll_params->vco_min = pll_params->adjust_vco(pll_params, in tegra_clk_register_pllre_tegra210()
2424 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_pllre_tegra210()
2587 struct tegra_clk_pll_params *pll_params, in tegra_clk_register_plle_tegra210() argument
2593 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); in tegra_clk_register_plle_tegra210()
2610 struct tegra_clk_pll_params *pll_params, in tegra_clk_register_pllc_tegra210() argument
2614 const struct pdiv_map *p_tohw = pll_params->pdiv_tohw; in tegra_clk_register_pllc_tegra210()
2630 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllc_tegra210()
2632 if (pll_params->adjust_vco) in tegra_clk_register_pllc_tegra210()
2633 pll_params->vco_min = pll_params->adjust_vco(pll_params, in tegra_clk_register_pllc_tegra210()
2636 pll_params->flags |= TEGRA_PLL_BYPASS; in tegra_clk_register_pllc_tegra210()
2637 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_pllc_tegra210()
2652 struct tegra_clk_pll_params *pll_params, in tegra_clk_register_pllss_tegra210() argument
2660 if (!pll_params->div_nmp) in tegra_clk_register_pllss_tegra210()
2670 val = readl_relaxed(clk_base + pll_params->base_reg); in tegra_clk_register_pllss_tegra210()
2678 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllss_tegra210()
2680 if (pll_params->adjust_vco) in tegra_clk_register_pllss_tegra210()
2681 pll_params->vco_min = pll_params->adjust_vco(pll_params, in tegra_clk_register_pllss_tegra210()
2684 pll_params->flags |= TEGRA_PLL_BYPASS; in tegra_clk_register_pllss_tegra210()
2685 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); in tegra_clk_register_pllss_tegra210()
2701 struct tegra_clk_pll_params *pll_params, in tegra_clk_register_pllmb() argument
2708 if (!pll_params->pdiv_tohw) in tegra_clk_register_pllmb()
2720 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllmb()
2722 if (pll_params->adjust_vco) in tegra_clk_register_pllmb()
2723 pll_params->vco_min = pll_params->adjust_vco(pll_params, in tegra_clk_register_pllmb()
2726 pll_params->flags |= TEGRA_PLL_BYPASS; in tegra_clk_register_pllmb()
2727 pll_params->flags |= TEGRA_PLLMB; in tegra_clk_register_pllmb()
2728 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_pllmb()