526 	for (sel = pll->params->freq_table; sel->input_rate != 0; sel++)  in _get_table_rate()
527 		if (sel->input_rate == parent_rate &&  in _get_table_rate()
531 	if (sel->input_rate == 0)  in _get_table_rate()
542 	cfg->input_rate = sel->input_rate;  in _get_table_rate()
956 	unsigned long input_rate;  in clk_plle_enable()  local
963 	input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));  in clk_plle_enable()
965 	if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))  in clk_plle_enable()
1119 	unsigned long flags = 0, input_rate;  in clk_pllu_enable()  local
1129 	input_rate = clk_hw_get_rate(osc);  in clk_pllu_enable()
1141 		if (input_rate == utmi_parameters[i].osc_frequency) {  in clk_pllu_enable()
1149 		       input_rate);  in clk_pllu_enable()
1231 	cfg->input_rate = parent_rate;  in _calc_dynamic_ramp_rate()
1250 u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate)  in tegra_pll_get_fixed_mdiv()  argument
1254 	return (u16)_pll_fixed_mdiv(pll->params, input_rate);  in tegra_pll_get_fixed_mdiv()
1449 					unsigned long input_rate, u32 n)  in _pllcx_update_dynamic_coef()  argument
1453 	switch (input_rate) {  in _pllcx_update_dynamic_coef()
1469 			__func__, input_rate);  in _pllcx_update_dynamic_coef()
1612 	unsigned long input_rate;  in clk_plle_tegra114_enable()  local
1614 	input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));  in clk_plle_tegra114_enable()
1616 	if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))  in clk_plle_tegra114_enable()
1741 	unsigned long flags = 0, input_rate;  in clk_pllu_tegra114_enable()  local
1754 	input_rate = clk_hw_get_rate(__clk_get_hw(osc));  in clk_pllu_tegra114_enable()
1766 		if (input_rate == utmi_parameters[i].osc_frequency) {  in clk_pllu_tegra114_enable()
1774 		       input_rate);  in clk_pllu_tegra114_enable()
2453 	unsigned long input_rate;  in clk_plle_tegra210_enable()  local
2458 	input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));  in clk_plle_tegra210_enable()
2460 	if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))  in clk_plle_tegra210_enable()