Lines Matching refs:divn_shift

253 #define divn_shift(p) (p)->params->div_nmp->divn_shift  macro
257 #define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p))
268 	.divn_shift = PLL_BASE_DIVN_SHIFT,
680 		       (cfg->n << divn_shift(pll)) |  in _update_pll_mnp()
711 		cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll);  in _get_pll_mnp()
988 		val |= sel.n << divn_shift(pll);  in clk_plle_enable()
1022 	divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll));  in clk_plle_recalc_rate()
1650 	val |= sel.n << divn_shift(pll);  in clk_plle_tegra114_enable()
1941 	.divn_shift = PLLE_BASE_DIVN_SHIFT,
2135 		val |= (pll_params->vco_min / parent_rate) << divn_shift(pll);  in tegra_clk_register_pllre()
2492 	val |= sel.n << divn_shift(pll);  in clk_plle_tegra210_enable()