Lines Matching +full:- +full:dig +full:- +full:div
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Based on ccu-sun8i-h3.c, which is:
9 #include <linux/clk-provider.h>
26 #include "ccu-sun8i-v3s.h"
28 static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu",
48 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
56 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
68 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
80 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
89 static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph0_clk, "pll-periph0",
95 2, /* post-div */
98 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_isp_clk, "pll-isp",
110 static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph1_clk, "pll-periph1",
116 2, /* post-div */
119 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1",
128 "pll-cpu", "pll-cpu" };
135 "axi", "pll-periph0" };
140 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
161 { .val = 0, .div = 2 },
162 { .val = 1, .div = 2 },
163 { .val = 2, .div = 4 },
164 { .val = 3, .div = 8 },
171 "pll-periph0", "pll-periph0" };
178 static const char * const ahb2_parents[] = { "ahb1", "pll-periph0" };
180 { .index = 1, .div = 2 },
200 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1",
202 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
204 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
206 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
208 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
210 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
212 static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb2",
214 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
216 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
218 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
220 static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb1",
222 static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb1",
225 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1",
227 static SUNXI_CCU_GATE(bus_tcon0_clk, "bus-tcon0", "ahb1",
229 static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1",
231 static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1",
234 static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1",
236 static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",
238 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
241 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
243 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
245 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
247 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
249 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
252 static SUNXI_CCU_GATE(bus_ephy_clk, "bus-ephy", "ahb1",
254 static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "ahb1",
257 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0",
258 "pll-periph1" };
295 static const char * const ce_parents[] = { "osc24M", "pll-periph0", };
311 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
312 "pll-audio-2x", "pll-audio" };
316 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
318 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc24M",
321 static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1",
322 "pll-periph0-2x" };
326 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram",
328 static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram",
330 static SUNXI_CCU_GATE(dram_ehci_clk, "dram-ehci", "dram",
332 static SUNXI_CCU_GATE(dram_ohci_clk, "dram-ohci", "dram",
335 static const char * const de_parents[] = { "pll-video", "pll-periph0" };
340 static const char * const tcon_parents[] = { "pll-video" };
344 static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M",
347 static const char * const csi_mclk_parents[] = { "osc24M", "pll-video",
348 "pll-periph0", "pll-periph1" };
349 static SUNXI_CCU_M_WITH_MUX_GATE(csi0_mclk_clk, "csi0-mclk", csi_mclk_parents,
352 static const char * const csi1_sclk_parents[] = { "pll-video", "pll-isp" };
353 static SUNXI_CCU_M_WITH_MUX_GATE(csi1_sclk_clk, "csi-sclk", csi1_sclk_parents,
356 static SUNXI_CCU_M_WITH_MUX_GATE(csi1_mclk_clk, "csi-mclk", csi_mclk_parents,
359 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
362 static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio",
367 static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x",
368 "pll-ddr" };
372 static const char * const mipi_csi_parents[] = { "pll-video", "pll-periph0",
373 "pll-isp" };
374 static SUNXI_CCU_M_WITH_MUX_GATE(mipi_csi_clk, "mipi-csi", mipi_csi_parents,
528 static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
531 static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
534 static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
537 static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
540 static CLK_FIXED_FACTOR_HW(pll_periph0_2x_clk, "pll-periph0-2x",
809 /* Force the PLL-Audio-1x divider to 4 */ in sun8i_v3_v3s_ccu_init()
827 CLK_OF_DECLARE(sun8i_v3s_ccu, "allwinner,sun8i-v3s-ccu",
830 CLK_OF_DECLARE(sun8i_v3_ccu, "allwinner,sun8i-v3-ccu",