Lines Matching +full:tcon +full:- +full:top +full:- +full:dsi

1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
24 #include "ccu-sun8i-r40.h"
36 .hw.init = CLK_HW_INIT("pll-cpu",
48 * With sigma-delta modulation for fractional-N on the audio PLL,
62 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
72 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video0_clk, "pll-video0",
87 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
100 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
119 .hw.init = CLK_HW_INIT("pll-periph0", "osc24M",
129 * The formula of pll-periph0 (1x) is 24MHz*N*K/2, and the formula
130 * of pll-periph0-sata is 24MHz*N*K/M/6, so the postdiv here is
137 .hw.init = CLK_HW_INIT("pll-periph0-sata",
138 "pll-periph0",
153 .hw.init = CLK_HW_INIT("pll-periph1", "osc24M",
159 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video1_clk, "pll-video1",
183 .hw.init = CLK_HW_INIT("pll-sata", "osc24M",
189 static const char * const pll_sata_out_parents[] = { "pll-sata",
190 "pll-periph0-sata" };
191 static SUNXI_CCU_MUX_WITH_GATE(pll_sata_out_clk, "pll-sata-out",
198 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
213 * The MIPI mode is a standard NKM-style clock. The HDMI mode is an
222 static const char * const pll_mipi_parents[] = { "pll-video0" };
232 .hw.init = CLK_HW_INIT_PARENTS("pll-mipi",
240 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
253 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1",
262 "pll-cpu", "pll-cpu" };
269 "axi", "pll-periph0" };
305 "pll-periph0-2x",
306 "pll-periph0-2x" };
313 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
315 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1",
317 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
319 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
321 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
323 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
325 static SUNXI_CCU_GATE(bus_mmc3_clk, "bus-mmc3", "ahb1",
327 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
329 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
331 static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb1",
333 static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb1",
335 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
337 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
339 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1",
341 static SUNXI_CCU_GATE(bus_spi2_clk, "bus-spi2", "ahb1",
343 static SUNXI_CCU_GATE(bus_spi3_clk, "bus-spi3", "ahb1",
345 static SUNXI_CCU_GATE(bus_sata_clk, "bus-sata", "ahb1",
347 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
349 static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb1",
351 static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb1",
353 static SUNXI_CCU_GATE(bus_ehci2_clk, "bus-ehci2", "ahb1",
355 static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb1",
357 static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb1",
359 static SUNXI_CCU_GATE(bus_ohci2_clk, "bus-ohci2", "ahb1",
362 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1",
364 static SUNXI_CCU_GATE(bus_mp_clk, "bus-mp", "ahb1",
366 static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "ahb1",
368 static SUNXI_CCU_GATE(bus_csi0_clk, "bus-csi0", "ahb1",
370 static SUNXI_CCU_GATE(bus_csi1_clk, "bus-csi1", "ahb1",
372 static SUNXI_CCU_GATE(bus_hdmi0_clk, "bus-hdmi0", "ahb1",
374 static SUNXI_CCU_GATE(bus_hdmi1_clk, "bus-hdmi1", "ahb1",
376 static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1",
378 static SUNXI_CCU_GATE(bus_tve0_clk, "bus-tve0", "ahb1",
380 static SUNXI_CCU_GATE(bus_tve1_clk, "bus-tve1", "ahb1",
382 static SUNXI_CCU_GATE(bus_tve_top_clk, "bus-tve-top", "ahb1",
384 static SUNXI_CCU_GATE(bus_gmac_clk, "bus-gmac", "ahb1",
386 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",
388 static SUNXI_CCU_GATE(bus_tvd0_clk, "bus-tvd0", "ahb1",
390 static SUNXI_CCU_GATE(bus_tvd1_clk, "bus-tvd1", "ahb1",
392 static SUNXI_CCU_GATE(bus_tvd2_clk, "bus-tvd2", "ahb1",
394 static SUNXI_CCU_GATE(bus_tvd3_clk, "bus-tvd3", "ahb1",
396 static SUNXI_CCU_GATE(bus_tvd_top_clk, "bus-tvd-top", "ahb1",
398 static SUNXI_CCU_GATE(bus_tcon_lcd0_clk, "bus-tcon-lcd0", "ahb1",
400 static SUNXI_CCU_GATE(bus_tcon_lcd1_clk, "bus-tcon-lcd1", "ahb1",
402 static SUNXI_CCU_GATE(bus_tcon_tv0_clk, "bus-tcon-tv0", "ahb1",
404 static SUNXI_CCU_GATE(bus_tcon_tv1_clk, "bus-tcon-tv1", "ahb1",
406 static SUNXI_CCU_GATE(bus_tcon_top_clk, "bus-tcon-top", "ahb1",
409 static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1",
411 static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1",
413 static SUNXI_CCU_GATE(bus_ac97_clk, "bus-ac97", "apb1",
415 static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",
417 static SUNXI_CCU_GATE(bus_ir0_clk, "bus-ir0", "apb1",
419 static SUNXI_CCU_GATE(bus_ir1_clk, "bus-ir1", "apb1",
421 static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1",
423 static SUNXI_CCU_GATE(bus_keypad_clk, "bus-keypad", "apb1",
425 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
427 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1",
429 static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1",
432 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
434 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
436 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
438 static SUNXI_CCU_GATE(bus_i2c3_clk, "bus-i2c3", "apb2",
444 static SUNXI_CCU_GATE(bus_can_clk, "bus-can", "apb2",
446 static SUNXI_CCU_GATE(bus_scr_clk, "bus-scr", "apb2",
448 static SUNXI_CCU_GATE(bus_ps20_clk, "bus-ps20", "apb2",
450 static SUNXI_CCU_GATE(bus_ps21_clk, "bus-ps21", "apb2",
452 static SUNXI_CCU_GATE(bus_i2c4_clk, "bus-i2c4", "apb2",
454 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
456 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
458 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
460 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
462 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2",
464 static SUNXI_CCU_GATE(bus_uart5_clk, "bus-uart5", "apb2",
466 static SUNXI_CCU_GATE(bus_uart6_clk, "bus-uart6", "apb2",
468 static SUNXI_CCU_GATE(bus_uart7_clk, "bus-uart7", "apb2",
471 static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "ahb1",
488 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0",
489 "pll-periph1" };
525 static const char * const ts_parents[] = { "osc24M", "pll-periph0", };
533 static const char * const ce_parents[] = { "osc24M", "pll-periph0-2x",
534 "pll-periph1-2x" };
570 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
571 "pll-audio-2x", "pll-audio" };
603 static const char * const sata_parents[] = { "pll-sata-out", "sata-ext" };
613 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
615 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
617 static SUNXI_CCU_GATE(usb_phy2_clk, "usb-phy2", "osc24M",
619 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M",
621 static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "osc12M",
623 static SUNXI_CCU_GATE(usb_ohci2_clk, "usb-ohci2", "osc12M",
626 static const char * const ir_parents[] = { "osc24M", "pll-periph0",
627 "pll-periph1", "osc32k" };
642 static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" };
646 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram",
648 static SUNXI_CCU_GATE(dram_csi0_clk, "dram-csi0", "dram",
650 static SUNXI_CCU_GATE(dram_csi1_clk, "dram-csi1", "dram",
652 static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "dram",
654 static SUNXI_CCU_GATE(dram_tvd_clk, "dram-tvd", "dram",
656 static SUNXI_CCU_GATE(dram_mp_clk, "dram-mp", "dram",
658 static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace", "dram",
661 static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
668 static const char * const tcon_parents[] = { "pll-video0", "pll-video1",
669 "pll-video0-2x", "pll-video1-2x",
670 "pll-mipi" };
671 static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd0_clk, "tcon-lcd0", tcon_parents,
673 static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd1_clk, "tcon-lcd1", tcon_parents,
675 static SUNXI_CCU_M_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0", tcon_parents,
678 static SUNXI_CCU_M_WITH_MUX_GATE(tcon_tv1_clk, "tcon-tv1", tcon_parents,
682 static const char * const deinterlace_parents[] = { "pll-periph0",
683 "pll-periph1" };
688 static const char * const csi_mclk_parents[] = { "osc24M", "pll-video1",
689 "pll-periph1" };
690 static SUNXI_CCU_M_WITH_MUX_GATE(csi1_mclk_clk, "csi1-mclk", csi_mclk_parents,
693 static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" };
694 static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents,
697 static SUNXI_CCU_M_WITH_MUX_GATE(csi0_mclk_clk, "csi0-mclk", csi_mclk_parents,
700 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
703 static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio",
708 static const char * const hdmi_parents[] = { "pll-video0", "pll-video1" };
713 static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M",
723 static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x",
724 "pll-ddr0" };
732 static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-video1",
733 "pll-periph0" };
734 static SUNXI_CCU_M_WITH_MUX_GATE(dsi_dphy_clk, "dsi-dphy", dsi_dphy_parents,
742 static const char * const tvd_parents[] = { "pll-video0", "pll-video1",
743 "pll-video0-2x", "pll-video1-2x" };
753 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
967 static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
970 static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
973 static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
976 static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
979 static CLK_FIXED_FACTOR_HW(pll_periph0_2x_clk, "pll-periph0-2x",
982 static CLK_FIXED_FACTOR_HW(pll_periph1_2x_clk, "pll-periph1-2x",
985 static CLK_FIXED_FACTOR_HW(pll_video0_2x_clk, "pll-video0-2x",
988 static CLK_FIXED_FACTOR_HW(pll_video1_2x_clk, "pll-video1-2x",
1279 * Add a regmap for the GMAC driver (dwmac-sun8i) to access the
1317 reg = devm_ioremap_resource(&pdev->dev, res); in sun8i_r40_ccu_probe()
1321 /* Force the PLL-Audio-1x divider to 1 */ in sun8i_r40_ccu_probe()
1326 /* Force PLL-MIPI to MIPI mode */ in sun8i_r40_ccu_probe()
1344 regmap = devm_regmap_init_mmio(&pdev->dev, reg, in sun8i_r40_ccu_probe()
1349 ret = sunxi_ccu_probe(pdev->dev.of_node, reg, &sun8i_r40_ccu_desc); in sun8i_r40_ccu_probe()
1364 { .compatible = "allwinner,sun8i-r40-ccu" },
1371 .name = "sun8i-r40-ccu",