Lines Matching +full:0 +full:x28
43 .reg = 0x00,
48 0),
52 static CLK_FIXED_FACTOR_HW(ahb0_clk, "ahb0", &ar100_clk.common.hw, 1, 1, 0);
54 static SUNXI_CCU_M(apb0_clk, "apb0", "ahb0", 0x0c, 0, 2, 0);
63 apb0_gate_parent, 0x28, BIT(0), 0);
65 apb0_gate_parent, 0x28, BIT(1), 0);
67 apb0_gate_parent, 0x28, BIT(2), 0);
69 apb0_gate_parent, 0x28, BIT(3), 0);
71 apb0_gate_parent, 0x28, BIT(4), 0);
73 apb0_gate_parent, 0x28, BIT(6), 0);
75 apb0_gate_parent, 0x28, BIT(7), 0);
79 r_mod0_default_parents, 0x54,
80 0, 4, /* M */
84 0);
91 { .index = 0, .div = 16 },
96 .m = _SUNXI_CCU_DIV(0, 4),
107 .reg = 0x54,
112 0),
205 [RST_APB0_IR] = { 0xb0, BIT(1) },
206 [RST_APB0_TIMER] = { 0xb0, BIT(2) },
207 [RST_APB0_RSB] = { 0xb0, BIT(3) },
208 [RST_APB0_UART] = { 0xb0, BIT(4) },
209 [RST_APB0_I2C] = { 0xb0, BIT(6) },
213 [RST_APB0_IR] = { 0xb0, BIT(1) },
214 [RST_APB0_TIMER] = { 0xb0, BIT(2) },
215 [RST_APB0_UART] = { 0xb0, BIT(4) },
216 [RST_APB0_I2C] = { 0xb0, BIT(6) },
220 [RST_APB0_IR] = { 0xb0, BIT(1) },
221 [RST_APB0_TIMER] = { 0xb0, BIT(2) },
222 [RST_APB0_RSB] = { 0xb0, BIT(3) },
223 [RST_APB0_UART] = { 0xb0, BIT(4) },
224 [RST_APB0_I2C] = { 0xb0, BIT(6) },
262 reg = of_io_request_and_map(node, 0, of_node_full_name(node)); in sunxi_r_ccu_init()