Lines Matching +full:- +full:dig +full:- +full:div
1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
23 #include "ccu-sun8i-a23-a33.h"
36 .hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
47 * With sigma-delta modulation for fractional-N on the audio PLL,
61 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
71 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
83 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
95 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
104 static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph_clk, "pll-periph",
110 2, /* post-div */
113 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
128 * The MIPI mode is a standard NKM-style clock. The HDMI mode is an
133 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_mipi_clk, "pll-mipi",
134 "pll-video", 0x040,
142 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic",
154 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
172 .hw.init = CLK_HW_INIT("pll-ddr1", "osc24M",
179 "pll-cpux" , "pll-cpux" };
186 "axi" , "pll-periph" };
191 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
212 { .val = 0, .div = 2 },
213 { .val = 1, .div = 2 },
214 { .val = 2, .div = 4 },
215 { .val = 3, .div = 8 },
222 "pll-periph" , "pll-periph" };
229 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
231 static SUNXI_CCU_GATE(bus_ss_clk, "bus-ss", "ahb1",
233 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
235 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
237 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
239 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
241 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
243 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
245 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
247 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
249 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1",
251 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
253 static SUNXI_CCU_GATE(bus_ehci_clk, "bus-ehci", "ahb1",
255 static SUNXI_CCU_GATE(bus_ohci_clk, "bus-ohci", "ahb1",
258 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1",
260 static SUNXI_CCU_GATE(bus_lcd_clk, "bus-lcd", "ahb1",
262 static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1",
264 static SUNXI_CCU_GATE(bus_de_be_clk, "bus-de-be", "ahb1",
266 static SUNXI_CCU_GATE(bus_de_fe_clk, "bus-de-fe", "ahb1",
268 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",
270 static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",
272 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
274 static SUNXI_CCU_GATE(bus_drc_clk, "bus-drc", "ahb1",
276 static SUNXI_CCU_GATE(bus_sat_clk, "bus-sat", "ahb1",
279 static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1",
281 static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",
283 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
285 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1",
288 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
290 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
292 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
294 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
296 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
298 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
300 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
302 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2",
305 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" };
370 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
371 "pll-audio-2x", "pll-audio" };
379 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
381 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
383 static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic",
385 static SUNXI_CCU_GATE(usb_hsic_12M_clk, "usb-hsic-12M", "osc24M",
387 static SUNXI_CCU_GATE(usb_ohci_clk, "usb-ohci", "osc24M",
390 static SUNXI_CCU_M(dram_clk, "dram", "pll-ddr",
393 static const char * const pll_ddr_parents[] = { "pll-ddr0", "pll-ddr1" };
394 static SUNXI_CCU_MUX(pll_ddr_clk, "pll-ddr", pll_ddr_parents,
397 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram",
399 static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram",
401 static SUNXI_CCU_GATE(dram_drc_clk, "dram-drc", "dram",
403 static SUNXI_CCU_GATE(dram_de_fe_clk, "dram-de-fe", "dram",
405 static SUNXI_CCU_GATE(dram_de_be_clk, "dram-de-be", "dram",
408 static const char * const de_parents[] = { "pll-video", "pll-periph-2x",
409 "pll-gpu", "pll-de" };
411 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_be_clk, "de-be",
415 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_fe_clk, "de-fe",
419 static const char * const lcd_ch0_parents[] = { "pll-video", "pll-video-2x",
420 "pll-mipi" };
422 static SUNXI_CCU_MUX_TABLE_WITH_GATE(lcd_ch0_clk, "lcd-ch0",
427 static const char * const lcd_ch1_parents[] = { "pll-video", "pll-video-2x" };
429 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(lcd_ch1_clk, "lcd-ch1",
433 static const char * const csi_sclk_parents[] = { "pll-video", "pll-de",
434 "pll-mipi", "pll-ve" };
436 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_sclk_clk, "csi-sclk",
440 static const char * const csi_mclk_parents[] = { "pll-video", "pll-de",
443 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_mclk_clk, "csi-mclk",
447 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
450 static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio",
452 static SUNXI_CCU_GATE(ac_dig_4x_clk, "ac-dig-4x", "pll-audio-4x",
457 static const char * const mbus_parents[] = { "osc24M", "pll-periph-2x",
458 "pll-ddr0", "pll-ddr1" };
462 static const char * const dsi_sclk_parents[] = { "pll-video", "pll-video-2x" };
464 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_sclk_clk, "dsi-sclk",
468 static const char * const dsi_dphy_parents[] = { "pll-video", "pll-periph" };
470 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy",
478 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
481 static const char * const ats_parents[] = { "osc24M", "pll-periph" };
588 static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
591 static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
594 static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
597 static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
600 static CLK_FIXED_FACTOR_HW(pll_periph_2x_clk, "pll-periph-2x",
603 static CLK_FIXED_FACTOR_HW(pll_video_2x_clk, "pll-video-2x",
798 /* Force the PLL-Audio-1x divider to 1 */ in sun8i_a33_ccu_setup()
803 /* Force PLL-MIPI to MIPI mode */ in sun8i_a33_ccu_setup()
817 CLK_OF_DECLARE(sun8i_a33_ccu, "allwinner,sun8i-a33-ccu",