Lines Matching +full:sun6i +full:- +full:a31 +full:- +full:codec
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
7 * Based on ccu-sun8i-h3.c by Maxime Ripard.
10 #include <linux/clk-provider.h>
29 #include "ccu-sun6i-a31.h"
31 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu",
45 * With sigma-delta modulation for fractional-N on the audio PLL,
47 * can no longer be used, as the audio codec requests the exact clock
59 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
69 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0",
81 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
93 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr",
102 static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph_clk, "pll-periph",
108 2, /* post-div */
111 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1",
123 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
138 * The MIPI mode is a standard NKM-style clock. The HDMI mode is an
144 static const char * const pll_mipi_parents[] = { "pll-video0", "pll-video1" };
145 static SUNXI_CCU_NKM_WITH_MUX_GATE_LOCK(pll_mipi_clk, "pll-mipi",
180 "pll-cpu", "pll-cpu" };
202 "axi", "pll-periph" };
240 "pll-periph", "pll-periph" };
247 static SUNXI_CCU_GATE(ahb1_mipidsi_clk, "ahb1-mipidsi", "ahb1",
249 static SUNXI_CCU_GATE(ahb1_ss_clk, "ahb1-ss", "ahb1",
251 static SUNXI_CCU_GATE(ahb1_dma_clk, "ahb1-dma", "ahb1",
253 static SUNXI_CCU_GATE(ahb1_mmc0_clk, "ahb1-mmc0", "ahb1",
255 static SUNXI_CCU_GATE(ahb1_mmc1_clk, "ahb1-mmc1", "ahb1",
257 static SUNXI_CCU_GATE(ahb1_mmc2_clk, "ahb1-mmc2", "ahb1",
259 static SUNXI_CCU_GATE(ahb1_mmc3_clk, "ahb1-mmc3", "ahb1",
261 static SUNXI_CCU_GATE(ahb1_nand1_clk, "ahb1-nand1", "ahb1",
263 static SUNXI_CCU_GATE(ahb1_nand0_clk, "ahb1-nand0", "ahb1",
265 static SUNXI_CCU_GATE(ahb1_sdram_clk, "ahb1-sdram", "ahb1",
267 static SUNXI_CCU_GATE(ahb1_emac_clk, "ahb1-emac", "ahb1",
269 static SUNXI_CCU_GATE(ahb1_ts_clk, "ahb1-ts", "ahb1",
271 static SUNXI_CCU_GATE(ahb1_hstimer_clk, "ahb1-hstimer", "ahb1",
273 static SUNXI_CCU_GATE(ahb1_spi0_clk, "ahb1-spi0", "ahb1",
275 static SUNXI_CCU_GATE(ahb1_spi1_clk, "ahb1-spi1", "ahb1",
277 static SUNXI_CCU_GATE(ahb1_spi2_clk, "ahb1-spi2", "ahb1",
279 static SUNXI_CCU_GATE(ahb1_spi3_clk, "ahb1-spi3", "ahb1",
281 static SUNXI_CCU_GATE(ahb1_otg_clk, "ahb1-otg", "ahb1",
283 static SUNXI_CCU_GATE(ahb1_ehci0_clk, "ahb1-ehci0", "ahb1",
285 static SUNXI_CCU_GATE(ahb1_ehci1_clk, "ahb1-ehci1", "ahb1",
287 static SUNXI_CCU_GATE(ahb1_ohci0_clk, "ahb1-ohci0", "ahb1",
289 static SUNXI_CCU_GATE(ahb1_ohci1_clk, "ahb1-ohci1", "ahb1",
291 static SUNXI_CCU_GATE(ahb1_ohci2_clk, "ahb1-ohci2", "ahb1",
294 static SUNXI_CCU_GATE(ahb1_ve_clk, "ahb1-ve", "ahb1",
296 static SUNXI_CCU_GATE(ahb1_lcd0_clk, "ahb1-lcd0", "ahb1",
298 static SUNXI_CCU_GATE(ahb1_lcd1_clk, "ahb1-lcd1", "ahb1",
300 static SUNXI_CCU_GATE(ahb1_csi_clk, "ahb1-csi", "ahb1",
302 static SUNXI_CCU_GATE(ahb1_hdmi_clk, "ahb1-hdmi", "ahb1",
304 static SUNXI_CCU_GATE(ahb1_be0_clk, "ahb1-be0", "ahb1",
306 static SUNXI_CCU_GATE(ahb1_be1_clk, "ahb1-be1", "ahb1",
308 static SUNXI_CCU_GATE(ahb1_fe0_clk, "ahb1-fe0", "ahb1",
310 static SUNXI_CCU_GATE(ahb1_fe1_clk, "ahb1-fe1", "ahb1",
312 static SUNXI_CCU_GATE(ahb1_mp_clk, "ahb1-mp", "ahb1",
314 static SUNXI_CCU_GATE(ahb1_gpu_clk, "ahb1-gpu", "ahb1",
316 static SUNXI_CCU_GATE(ahb1_deu0_clk, "ahb1-deu0", "ahb1",
318 static SUNXI_CCU_GATE(ahb1_deu1_clk, "ahb1-deu1", "ahb1",
320 static SUNXI_CCU_GATE(ahb1_drc0_clk, "ahb1-drc0", "ahb1",
322 static SUNXI_CCU_GATE(ahb1_drc1_clk, "ahb1-drc1", "ahb1",
325 static SUNXI_CCU_GATE(apb1_codec_clk, "apb1-codec", "apb1",
327 static SUNXI_CCU_GATE(apb1_spdif_clk, "apb1-spdif", "apb1",
329 static SUNXI_CCU_GATE(apb1_digital_mic_clk, "apb1-digital-mic", "apb1",
331 static SUNXI_CCU_GATE(apb1_pio_clk, "apb1-pio", "apb1",
333 static SUNXI_CCU_GATE(apb1_daudio0_clk, "apb1-daudio0", "apb1",
335 static SUNXI_CCU_GATE(apb1_daudio1_clk, "apb1-daudio1", "apb1",
338 static SUNXI_CCU_GATE(apb2_i2c0_clk, "apb2-i2c0", "apb2",
340 static SUNXI_CCU_GATE(apb2_i2c1_clk, "apb2-i2c1", "apb2",
342 static SUNXI_CCU_GATE(apb2_i2c2_clk, "apb2-i2c2", "apb2",
344 static SUNXI_CCU_GATE(apb2_i2c3_clk, "apb2-i2c3", "apb2",
346 static SUNXI_CCU_GATE(apb2_uart0_clk, "apb2-uart0", "apb2",
348 static SUNXI_CCU_GATE(apb2_uart1_clk, "apb2-uart1", "apb2",
350 static SUNXI_CCU_GATE(apb2_uart2_clk, "apb2-uart2", "apb2",
352 static SUNXI_CCU_GATE(apb2_uart3_clk, "apb2-uart3", "apb2",
354 static SUNXI_CCU_GATE(apb2_uart4_clk, "apb2-uart4", "apb2",
356 static SUNXI_CCU_GATE(apb2_uart5_clk, "apb2-uart5", "apb2",
359 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" };
469 static const char * const daudio_parents[] = { "pll-audio-8x", "pll-audio-4x",
470 "pll-audio-2x", "pll-audio" };
479 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
481 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
483 static SUNXI_CCU_GATE(usb_phy2_clk, "usb-phy2", "osc24M",
485 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc24M",
487 static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "osc24M",
489 static SUNXI_CCU_GATE(usb_ohci2_clk, "usb-ohci2", "osc24M",
494 static const char * const dram_parents[] = { "pll-ddr", "pll-periph" };
507 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "mdfs",
509 static SUNXI_CCU_GATE(dram_csi_isp_clk, "dram-csi-isp", "mdfs",
511 static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "mdfs",
513 static SUNXI_CCU_GATE(dram_drc0_clk, "dram-drc0", "mdfs",
515 static SUNXI_CCU_GATE(dram_drc1_clk, "dram-drc1", "mdfs",
517 static SUNXI_CCU_GATE(dram_deu0_clk, "dram-deu0", "mdfs",
519 static SUNXI_CCU_GATE(dram_deu1_clk, "dram-deu1", "mdfs",
521 static SUNXI_CCU_GATE(dram_fe0_clk, "dram-fe0", "mdfs",
523 static SUNXI_CCU_GATE(dram_fe1_clk, "dram-fe1", "mdfs",
525 static SUNXI_CCU_GATE(dram_be0_clk, "dram-be0", "mdfs",
527 static SUNXI_CCU_GATE(dram_be1_clk, "dram-be1", "mdfs",
529 static SUNXI_CCU_GATE(dram_mp_clk, "dram-mp", "mdfs",
532 static const char * const de_parents[] = { "pll-video0", "pll-video1",
533 "pll-periph-2x", "pll-gpu",
544 static const char * const mp_parents[] = { "pll-video0", "pll-video1",
549 static const char * const lcd_ch0_parents[] = { "pll-video0", "pll-video1",
550 "pll-video0-2x",
551 "pll-video1-2x", "pll-mipi" };
552 static SUNXI_CCU_MUX_WITH_GATE(lcd0_ch0_clk, "lcd0-ch0", lcd_ch0_parents,
554 static SUNXI_CCU_MUX_WITH_GATE(lcd1_ch0_clk, "lcd1-ch0", lcd_ch0_parents,
557 static const char * const lcd_ch1_parents[] = { "pll-video0", "pll-video1",
558 "pll-video0-2x",
559 "pll-video1-2x" };
560 static SUNXI_CCU_M_WITH_MUX_GATE(lcd0_ch1_clk, "lcd0-ch1", lcd_ch1_parents,
563 static SUNXI_CCU_M_WITH_MUX_GATE(lcd1_ch1_clk, "lcd1-ch1", lcd_ch1_parents,
567 static const char * const csi_sclk_parents[] = { "pll-video0", "pll-video1",
568 "pll9", "pll10", "pll-mipi",
569 "pll-ve" };
570 static SUNXI_CCU_M_WITH_MUX_GATE(csi0_sclk_clk, "csi0-sclk", csi_sclk_parents,
573 static const char * const csi_mclk_parents[] = { "pll-video0", "pll-video1",
582 .hw.init = CLK_HW_INIT_PARENTS("csi0-mclk",
595 .hw.init = CLK_HW_INIT_PARENTS("csi1-mclk",
602 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
605 static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio",
609 static SUNXI_CCU_GATE(digital_mic_clk, "digital-mic", "pll-audio",
618 static SUNXI_CCU_GATE(ps_clk, "ps", "lcd1-ch1", 0x140, BIT(31), 0);
620 static const char * const mbus_parents[] = { "osc24M", "pll-periph",
621 "pll-ddr" };
636 static SUNXI_CCU_M_WITH_MUX_GATE(mipi_dsi_clk, "mipi-dsi", lcd_ch1_parents,
639 static SUNXI_CCU_M_WITH_MUX_GATE(mipi_dsi_dphy_clk, "mipi-dsi-dphy",
642 static SUNXI_CCU_M_WITH_MUX_GATE(mipi_csi_dphy_clk, "mipi-csi-dphy",
646 static SUNXI_CCU_M_WITH_MUX_GATE(iep_drc0_clk, "iep-drc0", de_parents,
648 static SUNXI_CCU_M_WITH_MUX_GATE(iep_drc1_clk, "iep-drc1", de_parents,
650 static SUNXI_CCU_M_WITH_MUX_GATE(iep_deu0_clk, "iep-deu0", de_parents,
652 static SUNXI_CCU_M_WITH_MUX_GATE(iep_deu1_clk, "iep-deu1", de_parents,
655 static const char * const gpu_parents[] = { "pll-gpu", "pll-periph-2x",
656 "pll-video0", "pll-video1",
674 .hw.init = CLK_HW_INIT_PARENTS("gpu-core",
693 .hw.init = CLK_HW_INIT_PARENTS("gpu-memory",
712 .hw.init = CLK_HW_INIT_PARENTS("gpu-hyd",
756 .hw.init = CLK_HW_INIT_PARENTS("out-a",
777 .hw.init = CLK_HW_INIT_PARENTS("out-b",
798 .hw.init = CLK_HW_INIT_PARENTS("out-c",
963 static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
966 static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
969 static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
972 static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
975 static CLK_FIXED_FACTOR_HW(pll_periph_2x_clk, "pll-periph-2x",
978 static CLK_FIXED_FACTOR_HW(pll_video0_2x_clk, "pll-video0-2x",
981 static CLK_FIXED_FACTOR_HW(pll_video1_2x_clk, "pll-video1-2x",
1240 /* Force the PLL-Audio-1x divider to 1 */ in sun6i_a31_ccu_setup()
1245 /* Force PLL-MIPI to MIPI mode */ in sun6i_a31_ccu_setup()
1252 /* set PLL6 pre-div = 3 */ in sun6i_a31_ccu_setup()
1255 /* select PLL6 / pre-div */ in sun6i_a31_ccu_setup()
1265 CLK_OF_DECLARE(sun6i_a31_ccu, "allwinner,sun6i-a31-ccu",