Lines Matching +full:- +full:dig +full:- +full:div
1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
24 #include "ccu-sun50i-a64.h"
35 .hw.init = CLK_HW_INIT("pll-cpux",
47 * With sigma-delta modulation for fractional-N on the audio PLL,
61 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
71 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video0_clk, "pll-video0",
85 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
97 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
115 .hw.init = CLK_HW_INIT("pll-periph0", "osc24M",
129 .hw.init = CLK_HW_INIT("pll-periph1", "osc24M",
134 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video1_clk, "pll-video1",
148 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
181 .hw.init = CLK_HW_INIT("pll-mipi", "pll-video0",
186 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic",
198 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
210 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1",
219 "pll-cpux", "pll-cpux" };
226 "axi", "pll-periph0" };
231 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
252 { .val = 0, .div = 2 },
253 { .val = 1, .div = 2 },
254 { .val = 2, .div = 4 },
255 { .val = 3, .div = 8 },
262 "pll-periph0-2x",
263 "pll-periph0-2x" };
270 static const char * const ahb2_parents[] = { "ahb1", "pll-periph0" };
272 { .index = 1, .div = 2 },
292 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
294 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1",
296 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
298 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
300 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
302 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
304 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
306 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
308 static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb2",
310 static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb1",
312 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
314 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
316 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1",
318 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
320 static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb1",
322 static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb2",
324 static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb1",
326 static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb2",
329 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1",
331 static SUNXI_CCU_GATE(bus_tcon0_clk, "bus-tcon0", "ahb1",
333 static SUNXI_CCU_GATE(bus_tcon1_clk, "bus-tcon1", "ahb1",
335 static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "ahb1",
337 static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1",
339 static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb1",
341 static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1",
343 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",
345 static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",
347 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
350 static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1",
352 static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1",
354 static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",
356 static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1",
358 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
360 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1",
362 static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1",
365 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
367 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
369 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
371 static SUNXI_CCU_GATE(bus_scr_clk, "bus-scr", "apb2",
373 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
375 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
377 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
379 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
381 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2",
384 static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "ahb1",
388 { .val = 0, .div = 1 },
389 { .val = 1, .div = 2 },
390 { .val = 2, .div = 4 },
391 { .val = 3, .div = 6 },
396 .div = _SUNXI_CCU_DIV_TABLE(0, 2, ths_div_table),
407 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0",
408 "pll-periph1" };
427 static const char * const mmc_default_parents[] = { "osc24M", "pll-periph0-2x",
428 "pll-periph1-2x" };
435 2, /* post-div */
444 2, /* post-div */
453 2, /* post-div */
456 static const char * const ts_parents[] = { "osc24M", "pll-periph0", };
485 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
486 "pll-audio-2x", "pll-audio" };
496 static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio",
499 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
501 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
503 static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic",
505 static SUNXI_CCU_GATE(usb_hsic_12m_clk, "usb-hsic-12M", "osc12M",
507 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M",
509 static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "usb-ohci0",
512 static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" };
516 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram",
518 static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram",
520 static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace", "dram",
522 static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "dram",
525 static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
530 static const char * const tcon0_parents[] = { "pll-mipi", "pll-video0-2x" };
536 static const char * const tcon1_parents[] = { "pll-video0", "pll-video1" };
540 .div = _SUNXI_CCU_DIV(0, 4),
551 static const char * const deinterlace_parents[] = { "pll-periph0", "pll-periph1" };
555 static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M",
558 static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" };
559 static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents,
562 static const char * const csi_mclk_parents[] = { "osc24M", "pll-video1", "pll-periph1" };
563 static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents,
566 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
569 static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio",
572 static SUNXI_CCU_GATE(ac_dig_4x_clk, "ac-dig-4x", "pll-audio-4x",
578 static const char * const hdmi_parents[] = { "pll-video0", "pll-video1" };
582 static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M",
585 static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x",
586 "pll-ddr0", "pll-ddr1" };
590 static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-periph0" };
592 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy",
596 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
607 static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
610 static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
613 static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
616 static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
619 static CLK_FIXED_FACTOR_HW(pll_periph0_2x_clk, "pll-periph0-2x",
622 static CLK_FIXED_FACTOR_HW(pll_periph1_2x_clk, "pll-periph1-2x",
625 static CLK_FIXED_FACTOR_HW(pll_video0_2x_clk, "pll-video0-2x",
946 reg = devm_ioremap_resource(&pdev->dev, res); in sun50i_a64_ccu_probe()
950 /* Force the PLL-Audio-1x divider to 1 */ in sun50i_a64_ccu_probe()
957 ret = sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_a64_ccu_desc); in sun50i_a64_ccu_probe()
972 { .compatible = "allwinner,sun50i-a64-ccu" },
979 .name = "sun50i-a64-ccu",