Lines Matching +full:1 +full:mhz
24 #define SPEAR1340_HCLK_SRC_SEL_MASK 1
31 #define SPEAR1340_CLCD_SYNT_CLK_MASK 1
51 #define SPEAR1340_SPDIF_CLK_MASK 1
56 #define SPEAR1340_GPT_CLK_MASK 1
64 #define SPEAR1340_C3_CLK_MASK 1
65 #define SPEAR1340_C3_CLK_SHIFT 1
68 #define SPEAR1340_GMAC_PHY_CLK_MASK 1
86 #define SPEAR1340_I2S_REF_SEL_MASK 1
131 #define SPEAR1340_SYSROM_CLK_ENB 1
142 #define SPEAR1340_DDR_CORE_CLK_ENB 1
161 #define SPEAR1340_UART1_CLK_ENB 1
167 /* PCLK 24MHz */
168 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
169 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
170 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
171 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
172 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
173 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
174 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
175 {.mode = 0, .m = 0x96, .n = 0x06, .p = 0x0}, /* vco 1200, pll 1200 MHz */
180 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
181 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
182 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x2}, /* vco 1600, pll 400 MHz */
183 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
187 * All below entries generate 166 MHz for
191 {.div = 0x073A8}, /* for vco1div2 = 600 MHz */
192 {.div = 0x06062}, /* for vco1div2 = 500 MHz */
193 {.div = 0x04D1B}, /* for vco1div2 = 400 MHz */
194 {.div = 0x04000}, /* for vco1div2 = 332 MHz */
195 {.div = 0x03031}, /* for vco1div2 = 250 MHz */
196 {.div = 0x0268D}, /* for vco1div2 = 200 MHz */
205 * 250, 332, 400 or 500 MHz considering different possibilites of input
209 * vco1div2(Mhz) fout(Mhz) cpuclk = fout/2 div
266 /* 12.29MHz for vic1div2=600MHz and 10.24MHz for VCO1div2=500MHz */
268 /* 14.70MHz for vic1div2=600MHz and 12.29MHz for VCO1div2=500MHz */
270 /* 48MHz for vic1div2=600MHz and 40 MHz for VCO1div2=500MHz */
272 /* 57.14MHz for vic1div2=600MHz and 48 MHz for VCO1div2=500MHz */
274 /* 83.33MHz for vic1div2=600MHz and 69.44MHz for VCO1div2=500MHz */
276 /* 100MHz for vic1div2=600MHz and 83.33 MHz for VCO1div2=500MHz */
278 /* 125MHz for vic1div2=600MHz and 104.1MHz for VCO1div2=500MHz */
280 /* 150MHz for vic1div2=600MHz and 125MHz for VCO1div2=500MHz */
282 /* 166MHz for vic1div2=600MHz and 138.88MHz for VCO1div2=500MHz */
283 {.xscale = 5, .yscale = 18, .eq = 1},
284 /* 200MHz for vic1div2=600MHz and 166MHz for VCO1div2=500MHz */
285 {.xscale = 1, .yscale = 3, .eq = 1},
286 /* 250MHz for vic1div2=600MHz and 208.33MHz for VCO1div2=500MHz */
287 {.xscale = 5, .yscale = 12, .eq = 1},
288 /* 300MHz for vic1div2=600MHz and 250MHz for VCO1div2=500MHz */
289 {.xscale = 1, .yscale = 2, .eq = 1},
297 {.xscale = 1, .yscale = 3, .eq = 1}, /* divided by 3 */
298 {.xscale = 1, .yscale = 2, .eq = 1}, /* divided by 2 */
303 {.div = 0x18000}, /* 25 Mhz , for vc01div4 = 300 MHz*/
304 {.div = 0x1638E}, /* 27 Mhz , for vc01div4 = 300 MHz*/
305 {.div = 0x14000}, /* 25 Mhz , for vc01div4 = 250 MHz*/
306 {.div = 0x1284B}, /* 27 Mhz , for vc01div4 = 250 MHz*/
307 {.div = 0x0D8D3}, /* 58 Mhz , for vco1div4 = 393 MHz */
308 {.div = 0x0B72C}, /* 58 Mhz , for vco1div4 = 332 MHz */
309 {.div = 0x0A584}, /* 58 Mhz , for vco1div4 = 300 MHz */
310 {.div = 0x093B1}, /* 65 Mhz , for vc01div4 = 300 MHz*/
311 {.div = 0x089EE}, /* 58 Mhz , for vc01div4 = 250 MHz*/
312 {.div = 0x081BA}, /* 74 Mhz , for vc01div4 = 300 MHz*/
313 {.div = 0x07BA0}, /* 65 Mhz , for vc01div4 = 250 MHz*/
314 {.div = 0x06f1C}, /* 72 Mhz , for vc01div4 = 250 MHz*/
315 {.div = 0x06E58}, /* 58 Mhz , for vco1div4 = 200 MHz */
316 {.div = 0x06c1B}, /* 74 Mhz , for vc01div4 = 250 MHz*/
317 {.div = 0x058E3}, /* 108 Mhz , for vc01div4 = 300 MHz*/
318 {.div = 0x04A12}, /* 108 Mhz , for vc01div4 = 250 MHz*/
319 {.div = 0x040A5}, /* 148.5 Mhz , for vc01div4 = 300 MHz*/
320 {.div = 0x0378E}, /* 144 Mhz , for vc01div4 = 250 MHz*/
321 {.div = 0x0360D}, /* 148 Mhz , for vc01div4 = 250 MHz*/
322 {.div = 0x035E0}, /* 148.5 MHz, for vc01div4 = 250 MHz*/
352 /* For parent clk = 49.152 MHz */
353 {.xscale = 1, .yscale = 12, .eq = 0}, /* 2.048 MHz, smp freq = 8Khz */
354 {.xscale = 11, .yscale = 96, .eq = 0}, /* 2.816 MHz, smp freq = 11Khz */
355 {.xscale = 1, .yscale = 6, .eq = 0}, /* 4.096 MHz, smp freq = 16Khz */
356 {.xscale = 11, .yscale = 48, .eq = 0}, /* 5.632 MHz, smp freq = 22Khz */
359 * with parent clk = 49.152, freq gen is 8.192 MHz, smp freq = 32Khz
360 * with parent clk = 12.288, freq gen is 2.048 MHz, smp freq = 8Khz
362 {.xscale = 1, .yscale = 3, .eq = 0},
364 /* For parent clk = 49.152 MHz */
365 {.xscale = 17, .yscale = 37, .eq = 0}, /* 11.289 MHz, smp freq = 44Khz*/
366 {.xscale = 1, .yscale = 2, .eq = 0}, /* 12.288 MHz, smp freq = 48Khz*/
372 {.xscale = 1, .yscale = 4, .eq = 0},
373 {.xscale = 1, .yscale = 2, .eq = 0},
377 /* possible adc range is 2.5 MHz to 20 MHz. */
379 /* For ahb = 166.67 MHz */
380 {.xscale = 1, .yscale = 31, .eq = 0}, /* 2.68 MHz */
381 {.xscale = 2, .yscale = 21, .eq = 0}, /* 7.94 MHz */
382 {.xscale = 4, .yscale = 21, .eq = 0}, /* 15.87 MHz */
383 {.xscale = 10, .yscale = 42, .eq = 0}, /* 19.84 MHz */
388 {.div = 0x1A92B}, /* 22.5792 MHz for vco1div4=300 MHz*/
389 {.div = 0x186A0}, /* 24.576 MHz for vco1div4=300 MHz*/
390 {.div = 0x18000}, /* 25 MHz for vco1div4=300 MHz*/
391 {.div = 0x1624E}, /* 22.5792 MHz for vco1div4=250 MHz*/
392 {.div = 0x14585}, /* 24.576 MHz for vco1div4=250 MHz*/
393 {.div = 0x14000}, /* 25 MHz for vco1div4=250 MHz*/
394 {.div = 0x0D495}, /* 45.1584 MHz for vco1div4=300 MHz*/
395 {.div = 0x0C000}, /* 50 MHz for vco1div4=300 MHz*/
396 {.div = 0x0B127}, /* 45.1584 MHz for vco1div4=250 MHz*/
397 {.div = 0x0A000}, /* 50 MHz for vco1div4=250 MHz*/
398 {.div = 0x07530}, /* 81.92 MHz for vco1div4=300 MHz*/
399 {.div = 0x061A8}, /* 81.92 MHz for vco1div4=250 MHz*/
400 {.div = 0x06000}, /* 100 MHz for vco1div4=300 MHz*/
401 {.div = 0x05000}, /* 100 MHz for vco1div4=250 MHz*/
402 {.div = 0x03000}, /* 200 MHz for vco1div4=300 MHz*/
403 {.div = 0x02DB6}, /* 210 MHz for vco1div4=300 MHz*/
404 {.div = 0x02BA2}, /* 220 MHz for vco1div4=300 MHz*/
405 {.div = 0x029BD}, /* 230 MHz for vco1div4=300 MHz*/
406 {.div = 0x02800}, /* 200 MHz for vco1div4=250 MHz*/
407 {.div = 0x02666}, /* 250 MHz for vco1div4=300 MHz*/
408 {.div = 0x02620}, /* 210 MHz for vco1div4=250 MHz*/
409 {.div = 0x02460}, /* 220 MHz for vco1div4=250 MHz*/
410 {.div = 0x022C0}, /* 230 MHz for vco1div4=250 MHz*/
411 {.div = 0x02160}, /* 240 MHz for vco1div4=250 MHz*/
412 {.div = 0x02000}, /* 250 MHz for vco1div4=250 MHz*/
468 /* clock derived from 24 or 25 MHz osc clk */ in spear1340_clk_init()
518 clk = clk_register_fixed_factor(NULL, "vco1div2_clk", "vco1_clk", 0, 1, in spear1340_clk_init()
522 clk = clk_register_fixed_factor(NULL, "vco1div4_clk", "vco1_clk", 0, 1, in spear1340_clk_init()
526 clk = clk_register_fixed_factor(NULL, "vco2div2_clk", "vco2_clk", 0, 1, in spear1340_clk_init()
530 clk = clk_register_fixed_factor(NULL, "vco3div2_clk", "vco3_clk", 0, 1, in spear1340_clk_init()
535 clk_register_fixed_factor(NULL, "thermal_clk", "osc_24m_clk", 0, 1, in spear1340_clk_init()
543 clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1, in spear1340_clk_init()
544 1); in spear1340_clk_init()
564 clk = clk_register_fixed_factor(NULL, "cpu_clk", "sys_mclk", 0, 1, in spear1340_clk_init()
568 clk = clk_register_fixed_factor(NULL, "cpu_div3_clk", "cpu_clk", 0, 1, in spear1340_clk_init()
572 clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1, in spear1340_clk_init()
576 clk = clk_register_fixed_factor(NULL, "smp_twd_clk", "cpu_clk", 0, 1, in spear1340_clk_init()
586 clk = clk_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1, in spear1340_clk_init()
940 clk_register_clkdev(clk, NULL, "spear_cec.1"); in spear1340_clk_init()