Lines Matching full:mhz
234 /* PCLK 24MHz */
235 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
236 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
237 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
238 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
239 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
240 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
246 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
247 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
248 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x2}, /* vco 1600, pll 400 MHz */
254 /* For VCO1div2 = 500 MHz */
255 {.xscale = 10, .yscale = 204, .eq = 0}, /* 12.29 MHz */
256 {.xscale = 4, .yscale = 21, .eq = 0}, /* 48 MHz */
257 {.xscale = 2, .yscale = 6, .eq = 0}, /* 83 MHz */
258 {.xscale = 2, .yscale = 4, .eq = 0}, /* 125 MHz */
259 {.xscale = 1, .yscale = 3, .eq = 1}, /* 166 MHz */
260 {.xscale = 1, .yscale = 2, .eq = 1}, /* 250 MHz */
274 {.div = 0x14000}, /* 25 Mhz , for vc01div4 = 250 MHz*/
275 {.div = 0x1284B}, /* 27 Mhz , for vc01div4 = 250 MHz*/
276 {.div = 0x0D8D3}, /* 58 Mhz , for vco1div4 = 393 MHz */
277 {.div = 0x0B72C}, /* 58 Mhz , for vco1div4 = 332 MHz */
278 {.div = 0x089EE}, /* 58 Mhz , for vc01div4 = 250 MHz*/
279 {.div = 0x06f1C}, /* 72 Mhz , for vc01div4 = 250 MHz*/
280 {.div = 0x06E58}, /* 58 Mhz , for vco1div4 = 200 MHz */
281 {.div = 0x06c1B}, /* 74 Mhz , for vc01div4 = 250 MHz*/
282 {.div = 0x04A12}, /* 108 Mhz , for vc01div4 = 250 MHz*/
283 {.div = 0x0378E}, /* 144 Mhz , for vc01div4 = 250 MHz*/
313 /* For parent clk = 49.152 MHz */
314 {.xscale = 1, .yscale = 12, .eq = 0}, /* 2.048 MHz, smp freq = 8Khz */
315 {.xscale = 11, .yscale = 96, .eq = 0}, /* 2.816 MHz, smp freq = 11Khz */
316 {.xscale = 1, .yscale = 6, .eq = 0}, /* 4.096 MHz, smp freq = 16Khz */
317 {.xscale = 11, .yscale = 48, .eq = 0}, /* 5.632 MHz, smp freq = 22Khz */
320 * with parent clk = 49.152, freq gen is 8.192 MHz, smp freq = 32Khz
321 * with parent clk = 12.288, freq gen is 2.048 MHz, smp freq = 8Khz
325 /* For parent clk = 49.152 MHz */
326 {.xscale = 17, .yscale = 37, .eq = 0}, /* 11.289 MHz, smp freq = 44Khz*/
328 {.xscale = 1, .yscale = 2, .eq = 0}, /* 12.288 MHz */
333 /* For i2s_ref_clk = 12.288MHz */
334 {.xscale = 1, .yscale = 4, .eq = 0}, /* 1.53 MHz */
335 {.xscale = 1, .yscale = 2, .eq = 0}, /* 3.07 Mhz */
339 /* possible adc range is 2.5 MHz to 20 MHz. */
341 /* For ahb = 166.67 MHz */
342 {.xscale = 1, .yscale = 31, .eq = 0}, /* 2.68 MHz */
343 {.xscale = 2, .yscale = 21, .eq = 0}, /* 7.94 MHz */
344 {.xscale = 4, .yscale = 21, .eq = 0}, /* 15.87 MHz */
345 {.xscale = 10, .yscale = 42, .eq = 0}, /* 19.84 MHz */
350 /* For vco1div4 = 250 MHz */
351 {.div = 0x14000}, /* 25 MHz */
352 {.div = 0x0A000}, /* 50 MHz */
353 {.div = 0x05000}, /* 100 MHz */
354 {.div = 0x02000}, /* 250 MHz */
411 /* clock derived from 24 or 25 MHz osc clk */ in spear1310_clk_init()