Lines Matching +full:2 +full:c400000

10  * License version 2. This program is licensed "as is" without any
26 	#define SPEAR1310_RAS_SYNT2_3_CLK_MASK		2
28 	#define SPEAR1310_RAS_SYNT_CLK_MASK		2
30 	#define SPEAR1310_PLL_CLK_MASK			2
54 	#define SPEAR1310_UART_CLK_SYNT_VAL		2
55 	#define SPEAR1310_UART_CLK_MASK			2
60 	#define SPEAR1310_CLCD_CLK_MASK			2
61 	#define SPEAR1310_CLCD_CLK_SHIFT		2
70 	#define SPEAR1310_GMAC_PHY_INPUT_CLK_MASK	2
87 	#define SPEAR1310_I2S_REF_SHIFT			2
88 	#define SPEAR1310_I2S_SRC_CLK_MASK		2
134 	#define SPEAR1310_SYSRAM1_CLK_ENB		2
146 	#define SPEAR1310_CPU_DBG_CLK_ENB		2
167 	#define SPEAR1310_OSC_24M_CLK_ENB		2
200 	#define SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT	2
226 	#define SPEAR1310_MII1_CLK_ENB			2
257 	{.xscale = 2, .yscale = 6, .eq = 0}, /* 83 MHz */
258 	{.xscale = 2, .yscale = 4, .eq = 0}, /* 125 MHz */
260 	{.xscale = 1, .yscale = 2, .eq = 1}, /* 250 MHz */
266 	{.xscale = 2, .yscale = 6, .eq = 0}, /* divided by 6 */
267 	{.xscale = 2, .yscale = 4, .eq = 0}, /* divided by 4 */
269 	{.xscale = 1, .yscale = 2, .eq = 1}, /* divided by 2 */
328 	{.xscale = 1, .yscale = 2, .eq = 0}, /* 12.288 MHz */
335 	{.xscale = 1, .yscale = 2, .eq = 0}, /* 3.07 Mhz */
343 	{.xscale = 2, .yscale = 21, .eq = 0}, /* 7.94 MHz */
462 			2);  in spear1310_clk_init()
470 			2);  in spear1310_clk_init()
474 			2);  in spear1310_clk_init()
492 			CLK_SET_RATE_PARENT, 1, 2);  in spear1310_clk_init()
496 			2);  in spear1310_clk_init()
500 			2);  in spear1310_clk_init()
914 	clk_register_clkdev(clk, NULL, "5c400000.eth");  in spear1310_clk_init()
938 	clk_register_clkdev(clk, "stmmacphy.2", NULL);  in spear1310_clk_init()