Lines Matching refs:clk_phase
117 u32 clk_phase[2]; in socfpga_clk_prepare() local
119 if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) { in socfpga_clk_prepare()
127 switch (socfpgaclk->clk_phase[i]) { in socfpga_clk_prepare()
129 clk_phase[i] = 0; in socfpga_clk_prepare()
132 clk_phase[i] = 1; in socfpga_clk_prepare()
135 clk_phase[i] = 2; in socfpga_clk_prepare()
138 clk_phase[i] = 3; in socfpga_clk_prepare()
141 clk_phase[i] = 4; in socfpga_clk_prepare()
144 clk_phase[i] = 5; in socfpga_clk_prepare()
147 clk_phase[i] = 6; in socfpga_clk_prepare()
150 clk_phase[i] = 7; in socfpga_clk_prepare()
153 clk_phase[i] = 0; in socfpga_clk_prepare()
157 hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]); in socfpga_clk_prepare()
175 u32 clk_phase[2]; in socfpga_gate_init() local
220 rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2); in socfpga_gate_init()
222 socfpga_clk->clk_phase[0] = clk_phase[0]; in socfpga_gate_init()
223 socfpga_clk->clk_phase[1] = clk_phase[1]; in socfpga_gate_init()