1 // SPDX-License-Identifier: GPL-2.0
3  * Copyright (C) 2018-2019 SiFive, Inc.
17  * FU540-C000 chip.  This driver assumes that it has sole control
21  * https://github.com/riscv/riscv-linux/commit/999529edf517ed75b56659d456d221b2ee56bb60
24  * - SiFive FU540-C000 manual v1p0, Chapter 7 "Clocking and Reset"
27 #include <dt-bindings/clock/sifive-fu540-prci.h>
29 #include <linux/clk-provider.h>
30 #include <linux/clk/analogbits-wrpll-cln28hpc.h>
139  * struct __prci_data - per-device-instance data
143  * PRCI per-device instance data
151  * struct __prci_wrpll_data - WRPLL configuration and integration data
158  * that contain a separate external glitchless clock mux downstream
159  * from the PLL.  The WRPLL internal bypass mux is not glitchless.
169  * struct __prci_clock - describes a clock device managed by PRCI
170  * @name: user-readable clock name string - should match the manual
173  * @hw: Linux-private clock data
174  * @pwd: WRPLL-specific data, associated with this clock (if not NULL)
175  * @pd: PRCI-specific data associated with this clock (if not NULL)
177  * PRCI clock data.  Used by the PRCI driver to register PRCI-provided
196  * __prci_readl() - read from a PRCI register
210 	return readl_relaxed(pd->va + offs);  in __prci_readl()
215 	writel_relaxed(v, pd->va + offs);  in __prci_writel()
218 /* WRPLL-related private functions */
221  * __prci_wrpll_unpack() - unpack WRPLL configuration registers into parameters
240 	c->divr = v;  in __prci_wrpll_unpack()
244 	c->divf = v;  in __prci_wrpll_unpack()
248 	c->divq = v;  in __prci_wrpll_unpack()
252 	c->range = v;  in __prci_wrpll_unpack()
254 	c->flags &= (WRPLL_FLAGS_INT_FEEDBACK_MASK |  in __prci_wrpll_unpack()
258 	c->flags |= WRPLL_FLAGS_INT_FEEDBACK_MASK;  in __prci_wrpll_unpack()
262  * __prci_wrpll_pack() - pack PLL configuration parameters into a register value
280 	r |= c->divr << PRCI_COREPLLCFG0_DIVR_SHIFT;  in __prci_wrpll_pack()
281 	r |= c->divf << PRCI_COREPLLCFG0_DIVF_SHIFT;  in __prci_wrpll_pack()
282 	r |= c->divq << PRCI_COREPLLCFG0_DIVQ_SHIFT;  in __prci_wrpll_pack()
283 	r |= c->range << PRCI_COREPLLCFG0_RANGE_SHIFT;  in __prci_wrpll_pack()
292  * __prci_wrpll_read_cfg() - read the WRPLL configuration from the PRCI
306 	__prci_wrpll_unpack(&pwd->c, __prci_readl(pd, pwd->cfg0_offs));  in __prci_wrpll_read_cfg()
310  * __prci_wrpll_write_cfg() - write WRPLL configuration into the PRCI
327 	__prci_writel(__prci_wrpll_pack(c), pwd->cfg0_offs, pd);  in __prci_wrpll_write_cfg()
329 	memcpy(&pwd->c, c, sizeof(*c));  in __prci_wrpll_write_cfg()
332 /* Core clock mux control */
335  * __prci_coreclksel_use_hfclk() - switch the CORECLK mux to output HFCLK
336  * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
338  * Switch the CORECLK mux to the HFCLK input source; return once complete.
355  * __prci_coreclksel_use_corepll() - switch the CORECLK mux to output COREPLL
356  * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
358  * Switch the CORECLK mux to the PLL output clock; return once complete.
385 	struct __prci_wrpll_data *pwd = pc->pwd;  in sifive_fu540_prci_wrpll_recalc_rate()
387 	return wrpll_calc_output_rate(&pwd->c, parent_rate);  in sifive_fu540_prci_wrpll_recalc_rate()
395 	struct __prci_wrpll_data *pwd = pc->pwd;  in sifive_fu540_prci_wrpll_round_rate()
398 	memcpy(&c, &pwd->c, sizeof(c));  in sifive_fu540_prci_wrpll_round_rate()
410 	struct __prci_wrpll_data *pwd = pc->pwd;  in sifive_fu540_prci_wrpll_set_rate()
411 	struct __prci_data *pd = pc->pd;  in sifive_fu540_prci_wrpll_set_rate()
414 	r = wrpll_configure_for_rate(&pwd->c, rate, parent_rate);  in sifive_fu540_prci_wrpll_set_rate()
418 	if (pwd->enable_bypass)  in sifive_fu540_prci_wrpll_set_rate()
419 		pwd->enable_bypass(pd);  in sifive_fu540_prci_wrpll_set_rate()
421 	__prci_wrpll_write_cfg(pd, pwd, &pwd->c);  in sifive_fu540_prci_wrpll_set_rate()
423 	udelay(wrpll_calc_max_lock_us(&pwd->c));  in sifive_fu540_prci_wrpll_set_rate()
425 	if (pwd->disable_bypass)  in sifive_fu540_prci_wrpll_set_rate()
426 		pwd->disable_bypass(pd);  in sifive_fu540_prci_wrpll_set_rate()
447 	struct __prci_data *pd = pc->pd;  in sifive_fu540_prci_tlclksel_recalc_rate()
511  * __prci_register_clocks() - register clock controls in the PRCI with Linux
525 	parent_count = of_clk_get_parent_count(dev->of_node);  in __prci_register_clocks()
529 		return -EINVAL;  in __prci_register_clocks()
536 		init.name = pic->name;  in __prci_register_clocks()
537 		init.parent_names = &pic->parent_name;  in __prci_register_clocks()
539 		init.ops = pic->ops;  in __prci_register_clocks()
540 		pic->hw.init = &init;  in __prci_register_clocks()
542 		pic->pd = pd;  in __prci_register_clocks()
544 		if (pic->pwd)  in __prci_register_clocks()
545 			__prci_wrpll_read_cfg(pd, pic->pwd);  in __prci_register_clocks()
547 		r = devm_clk_hw_register(dev, &pic->hw);  in __prci_register_clocks()
554 		r = clk_hw_register_clkdev(&pic->hw, pic->name, dev_name(dev));  in __prci_register_clocks()
561 		pd->hw_clks.hws[i] = &pic->hw;  in __prci_register_clocks()
564 	pd->hw_clks.num = i;  in __prci_register_clocks()
567 					&pd->hw_clks);  in __prci_register_clocks()
584 	struct device *dev = &pdev->dev;  in sifive_fu540_prci_probe()
594 		return -ENOMEM;  in sifive_fu540_prci_probe()
597 	pd->va = devm_ioremap_resource(dev, res);  in sifive_fu540_prci_probe()
598 	if (IS_ERR(pd->va))  in sifive_fu540_prci_probe()
599 		return PTR_ERR(pd->va);  in sifive_fu540_prci_probe()
613 	{ .compatible = "sifive,fu540-c000-prci", },
620 		.name = "sifive-fu540-prci",