Lines Matching +full:1 +full:mhz
57 MUX(FCLK, "fclk", fclk_p, CLKSLOW, 4, 1),
61 { .val = 0, .div = 1 },
62 { .val = 1, .div = 2 },
74 DIV(PCLK, "pclk", "hclk", CLKDIVN, 0, 1),
123 PLL_S3C2410_MPLL_RATE(12 * MHZ, 270000000, 127, 1, 1),
124 PLL_S3C2410_MPLL_RATE(12 * MHZ, 268000000, 126, 1, 1),
125 PLL_S3C2410_MPLL_RATE(12 * MHZ, 266000000, 125, 1, 1),
126 PLL_S3C2410_MPLL_RATE(12 * MHZ, 226000000, 105, 1, 1),
127 PLL_S3C2410_MPLL_RATE(12 * MHZ, 210000000, 132, 2, 1),
129 PLL_S3C2410_MPLL_RATE(12 * MHZ, 202800000, 161, 3, 1),
130 PLL_S3C2410_MPLL_RATE(12 * MHZ, 192000000, 88, 1, 1),
131 PLL_S3C2410_MPLL_RATE(12 * MHZ, 186000000, 85, 1, 1),
132 PLL_S3C2410_MPLL_RATE(12 * MHZ, 180000000, 82, 1, 1),
133 PLL_S3C2410_MPLL_RATE(12 * MHZ, 170000000, 77, 1, 1),
134 PLL_S3C2410_MPLL_RATE(12 * MHZ, 158000000, 71, 1, 1),
135 PLL_S3C2410_MPLL_RATE(12 * MHZ, 152000000, 68, 1, 1),
136 PLL_S3C2410_MPLL_RATE(12 * MHZ, 147000000, 90, 2, 1),
137 PLL_S3C2410_MPLL_RATE(12 * MHZ, 135000000, 82, 2, 1),
138 PLL_S3C2410_MPLL_RATE(12 * MHZ, 124000000, 116, 1, 2),
139 PLL_S3C2410_MPLL_RATE(12 * MHZ, 118500000, 150, 2, 2),
140 PLL_S3C2410_MPLL_RATE(12 * MHZ, 113000000, 105, 1, 2),
141 PLL_S3C2410_MPLL_RATE(12 * MHZ, 101250000, 127, 2, 2),
142 PLL_S3C2410_MPLL_RATE(12 * MHZ, 90000000, 112, 2, 2),
143 PLL_S3C2410_MPLL_RATE(12 * MHZ, 84750000, 105, 2, 2),
144 PLL_S3C2410_MPLL_RATE(12 * MHZ, 79000000, 71, 1, 2),
145 PLL_S3C2410_MPLL_RATE(12 * MHZ, 67500000, 82, 2, 2),
146 PLL_S3C2410_MPLL_RATE(12 * MHZ, 56250000, 142, 2, 3),
147 PLL_S3C2410_MPLL_RATE(12 * MHZ, 48000000, 120, 2, 3),
148 PLL_S3C2410_MPLL_RATE(12 * MHZ, 50700000, 161, 3, 3),
149 PLL_S3C2410_MPLL_RATE(12 * MHZ, 45000000, 82, 1, 3),
150 PLL_S3C2410_MPLL_RATE(12 * MHZ, 33750000, 82, 2, 3),
162 DIV(HCLK, "hclk", "mpll", CLKDIVN, 1, 1),
170 FFACTOR(ARMCLK, "armclk", "fclk", 1, 1, 0),
173 FFACTOR(UCLK, "uclk", "upll", 1, 1, 0),
178 ALIAS(PCLK_UART1, "s3c2410-uart.1", "uart"),
181 ALIAS(PCLK_UART1, "s3c2410-uart.1", "clk_uart_baud0"),
190 PLL_S3C2440_MPLL_RATE(12 * MHZ, 400000000, 0x5c, 1, 1),
191 PLL_S3C2440_MPLL_RATE(12 * MHZ, 390000000, 0x7a, 2, 1),
192 PLL_S3C2440_MPLL_RATE(12 * MHZ, 380000000, 0x57, 1, 1),
193 PLL_S3C2440_MPLL_RATE(12 * MHZ, 370000000, 0xb1, 4, 1),
194 PLL_S3C2440_MPLL_RATE(12 * MHZ, 360000000, 0x70, 2, 1),
195 PLL_S3C2440_MPLL_RATE(12 * MHZ, 350000000, 0xa7, 4, 1),
196 PLL_S3C2440_MPLL_RATE(12 * MHZ, 340000000, 0x4d, 1, 1),
197 PLL_S3C2440_MPLL_RATE(12 * MHZ, 330000000, 0x66, 2, 1),
198 PLL_S3C2440_MPLL_RATE(12 * MHZ, 320000000, 0x98, 4, 1),
199 PLL_S3C2440_MPLL_RATE(12 * MHZ, 310000000, 0x93, 4, 1),
200 PLL_S3C2440_MPLL_RATE(12 * MHZ, 300000000, 0x75, 3, 1),
201 PLL_S3C2440_MPLL_RATE(12 * MHZ, 240000000, 0x70, 1, 2),
202 PLL_S3C2440_MPLL_RATE(12 * MHZ, 230000000, 0x6b, 1, 2),
203 PLL_S3C2440_MPLL_RATE(12 * MHZ, 220000000, 0x66, 1, 2),
204 PLL_S3C2440_MPLL_RATE(12 * MHZ, 210000000, 0x84, 2, 2),
205 PLL_S3C2440_MPLL_RATE(12 * MHZ, 200000000, 0x5c, 1, 2),
206 PLL_S3C2440_MPLL_RATE(12 * MHZ, 190000000, 0x57, 1, 2),
207 PLL_S3C2440_MPLL_RATE(12 * MHZ, 180000000, 0x70, 2, 2),
208 PLL_S3C2440_MPLL_RATE(12 * MHZ, 170000000, 0x4d, 1, 2),
209 PLL_S3C2440_MPLL_RATE(12 * MHZ, 160000000, 0x98, 4, 2),
210 PLL_S3C2440_MPLL_RATE(12 * MHZ, 150000000, 0x75, 3, 2),
211 PLL_S3C2440_MPLL_RATE(12 * MHZ, 120000000, 0x70, 1, 3),
212 PLL_S3C2440_MPLL_RATE(12 * MHZ, 110000000, 0x66, 1, 3),
213 PLL_S3C2440_MPLL_RATE(12 * MHZ, 100000000, 0x5c, 1, 3),
214 PLL_S3C2440_MPLL_RATE(12 * MHZ, 90000000, 0x70, 2, 3),
215 PLL_S3C2440_MPLL_RATE(12 * MHZ, 80000000, 0x98, 4, 3),
216 PLL_S3C2440_MPLL_RATE(12 * MHZ, 75000000, 0x75, 3, 3),
231 MUX(HCLK, "hclk", hclk_p, CLKDIVN, 1, 2),
232 MUX(ARMCLK, "armclk", armclk_p, CAMDIVN, 12, 1),
236 FFACTOR(0, "div_hclk_2", "fclk", 1, 2, 0),
237 FFACTOR(0, "ff_cam", "div_cam", 2, 1, CLK_SET_RATE_PARENT),
242 { .val = 1, .div = 8 },
248 { .val = 1, .div = 6 },
253 DIV(UCLK, "uclk", "upll", CLKDIVN, 3, 1),
254 DIV(0, "div_hclk", "fclk", CLKDIVN, 1, 1),
255 DIV_T(0, "div_hclk_4", "fclk", CAMDIVN, 9, 1, div_hclk_4_d),
256 DIV_T(0, "div_hclk_3", "fclk", CAMDIVN, 8, 1, div_hclk_3_d),
266 ALIAS(PCLK_UART1, "s3c2440-uart.1", "uart"),
269 ALIAS(PCLK_UART1, "s3c2440-uart.1", "clk_uart_baud2"),
280 MUX(CAMIF, "camif", s3c2440_camif_p, CAMDIVN, 4, 1),
290 FFACTOR(0, "upll_3", "upll", 1, 3, 0),
303 #define XTI 1
318 samsung_clk_register_alias(ctx, &xti_alias, 1); in s3c2410_common_clk_register_fixed_ext()
341 if (_get_rate("xti") == 12 * MHZ) { in s3c2410_common_clk_init()
351 if (_get_rate("xti") == 12 * MHZ) { in s3c2410_common_clk_init()