Lines Matching +full:hw +full:- +full:settle +full:- +full:time
1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/clk-provider.h>
16 #include "clk-pll.h"
21 struct clk_hw hw; member
33 #define to_clk_pll(_hw) container_of(_hw, struct samsung_clk_pll, hw)
38 const struct samsung_pll_rate_table *rate_table = pll->rate_table; in samsung_get_pll_settings()
41 for (i = 0; i < pll->rate_count; i++) { in samsung_get_pll_settings()
49 static long samsung_pll_round_rate(struct clk_hw *hw, in samsung_pll_round_rate() argument
52 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll_round_rate()
53 const struct samsung_pll_rate_table *rate_table = pll->rate_table; in samsung_pll_round_rate()
57 for (i = 0; i < pll->rate_count; i++) { in samsung_pll_round_rate()
63 return rate_table[i - 1].rate; in samsung_pll_round_rate()
66 static int samsung_pll3xxx_enable(struct clk_hw *hw) in samsung_pll3xxx_enable() argument
68 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll3xxx_enable()
71 tmp = readl_relaxed(pll->con_reg); in samsung_pll3xxx_enable()
72 tmp |= BIT(pll->enable_offs); in samsung_pll3xxx_enable()
73 writel_relaxed(tmp, pll->con_reg); in samsung_pll3xxx_enable()
75 /* wait lock time */ in samsung_pll3xxx_enable()
78 tmp = readl_relaxed(pll->con_reg); in samsung_pll3xxx_enable()
79 } while (!(tmp & BIT(pll->lock_offs))); in samsung_pll3xxx_enable()
84 static void samsung_pll3xxx_disable(struct clk_hw *hw) in samsung_pll3xxx_disable() argument
86 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll3xxx_disable()
89 tmp = readl_relaxed(pll->con_reg); in samsung_pll3xxx_disable()
90 tmp &= ~BIT(pll->enable_offs); in samsung_pll3xxx_disable()
91 writel_relaxed(tmp, pll->con_reg); in samsung_pll3xxx_disable()
105 static unsigned long samsung_pll2126_recalc_rate(struct clk_hw *hw, in samsung_pll2126_recalc_rate() argument
108 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2126_recalc_rate()
112 pll_con = readl_relaxed(pll->con_reg); in samsung_pll2126_recalc_rate()
138 static unsigned long samsung_pll3000_recalc_rate(struct clk_hw *hw, in samsung_pll3000_recalc_rate() argument
141 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll3000_recalc_rate()
145 pll_con = readl_relaxed(pll->con_reg); in samsung_pll3000_recalc_rate()
163 /* Maximum lock time can be 270 * PDIV cycles */
175 static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw, in samsung_pll35xx_recalc_rate() argument
178 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll35xx_recalc_rate()
182 pll_con = readl_relaxed(pll->con_reg); in samsung_pll35xx_recalc_rate()
201 return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv); in samsung_pll35xx_mp_change()
204 static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate, in samsung_pll35xx_set_rate() argument
207 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll35xx_set_rate()
215 drate, clk_hw_get_name(hw)); in samsung_pll35xx_set_rate()
216 return -EINVAL; in samsung_pll35xx_set_rate()
219 tmp = readl_relaxed(pll->con_reg); in samsung_pll35xx_set_rate()
224 tmp |= rate->sdiv << PLL35XX_SDIV_SHIFT; in samsung_pll35xx_set_rate()
225 writel_relaxed(tmp, pll->con_reg); in samsung_pll35xx_set_rate()
230 /* Set PLL lock time. */ in samsung_pll35xx_set_rate()
231 writel_relaxed(rate->pdiv * PLL35XX_LOCK_FACTOR, in samsung_pll35xx_set_rate()
232 pll->lock_reg); in samsung_pll35xx_set_rate()
238 tmp |= (rate->mdiv << PLL35XX_MDIV_SHIFT) | in samsung_pll35xx_set_rate()
239 (rate->pdiv << PLL35XX_PDIV_SHIFT) | in samsung_pll35xx_set_rate()
240 (rate->sdiv << PLL35XX_SDIV_SHIFT); in samsung_pll35xx_set_rate()
241 writel_relaxed(tmp, pll->con_reg); in samsung_pll35xx_set_rate()
244 if (tmp & BIT(pll->enable_offs)) { in samsung_pll35xx_set_rate()
247 tmp = readl_relaxed(pll->con_reg); in samsung_pll35xx_set_rate()
248 } while (!(tmp & BIT(pll->lock_offs))); in samsung_pll35xx_set_rate()
268 /* Maximum lock time can be 3000 * PDIV cycles */
282 static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw, in samsung_pll36xx_recalc_rate() argument
285 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll36xx_recalc_rate()
290 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll36xx_recalc_rate()
291 pll_con1 = readl_relaxed(pll->con_reg + 4); in samsung_pll36xx_recalc_rate()
313 return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv || in samsung_pll36xx_mpk_change()
314 rate->kdiv != old_kdiv); in samsung_pll36xx_mpk_change()
317 static int samsung_pll36xx_set_rate(struct clk_hw *hw, unsigned long drate, in samsung_pll36xx_set_rate() argument
320 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll36xx_set_rate()
327 drate, clk_hw_get_name(hw)); in samsung_pll36xx_set_rate()
328 return -EINVAL; in samsung_pll36xx_set_rate()
331 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll36xx_set_rate()
332 pll_con1 = readl_relaxed(pll->con_reg + 4); in samsung_pll36xx_set_rate()
337 pll_con0 |= (rate->sdiv << PLL36XX_SDIV_SHIFT); in samsung_pll36xx_set_rate()
338 writel_relaxed(pll_con0, pll->con_reg); in samsung_pll36xx_set_rate()
343 /* Set PLL lock time. */ in samsung_pll36xx_set_rate()
344 writel_relaxed(rate->pdiv * PLL36XX_LOCK_FACTOR, pll->lock_reg); in samsung_pll36xx_set_rate()
350 pll_con0 |= (rate->mdiv << PLL36XX_MDIV_SHIFT) | in samsung_pll36xx_set_rate()
351 (rate->pdiv << PLL36XX_PDIV_SHIFT) | in samsung_pll36xx_set_rate()
352 (rate->sdiv << PLL36XX_SDIV_SHIFT); in samsung_pll36xx_set_rate()
353 writel_relaxed(pll_con0, pll->con_reg); in samsung_pll36xx_set_rate()
356 pll_con1 |= rate->kdiv << PLL36XX_KDIV_SHIFT; in samsung_pll36xx_set_rate()
357 writel_relaxed(pll_con1, pll->con_reg + 4); in samsung_pll36xx_set_rate()
360 if (pll_con0 & BIT(pll->enable_offs)) { in samsung_pll36xx_set_rate()
363 tmp = readl_relaxed(pll->con_reg); in samsung_pll36xx_set_rate()
364 } while (!(tmp & BIT(pll->lock_offs))); in samsung_pll36xx_set_rate()
400 static unsigned long samsung_pll45xx_recalc_rate(struct clk_hw *hw, in samsung_pll45xx_recalc_rate() argument
403 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll45xx_recalc_rate()
407 pll_con = readl_relaxed(pll->con_reg); in samsung_pll45xx_recalc_rate()
412 if (pll->type == pll_4508) in samsung_pll45xx_recalc_rate()
413 sdiv = sdiv - 1; in samsung_pll45xx_recalc_rate()
430 return (old_mdiv != rate->mdiv || old_pdiv != rate->pdiv in samsung_pll45xx_mp_change()
431 || old_afc != rate->afc); in samsung_pll45xx_mp_change()
434 static int samsung_pll45xx_set_rate(struct clk_hw *hw, unsigned long drate, in samsung_pll45xx_set_rate() argument
437 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll45xx_set_rate()
446 drate, clk_hw_get_name(hw)); in samsung_pll45xx_set_rate()
447 return -EINVAL; in samsung_pll45xx_set_rate()
450 con0 = readl_relaxed(pll->con_reg); in samsung_pll45xx_set_rate()
451 con1 = readl_relaxed(pll->con_reg + 0x4); in samsung_pll45xx_set_rate()
456 con0 |= rate->sdiv << PLL45XX_SDIV_SHIFT; in samsung_pll45xx_set_rate()
457 writel_relaxed(con0, pll->con_reg); in samsung_pll45xx_set_rate()
466 con0 |= (rate->mdiv << PLL45XX_MDIV_SHIFT) | in samsung_pll45xx_set_rate()
467 (rate->pdiv << PLL45XX_PDIV_SHIFT) | in samsung_pll45xx_set_rate()
468 (rate->sdiv << PLL45XX_SDIV_SHIFT); in samsung_pll45xx_set_rate()
471 con1 = readl_relaxed(pll->con_reg + 0x4); in samsung_pll45xx_set_rate()
473 con1 |= (rate->afc << PLL45XX_AFC_SHIFT); in samsung_pll45xx_set_rate()
475 /* Set PLL lock time. */ in samsung_pll45xx_set_rate()
476 switch (pll->type) { in samsung_pll45xx_set_rate()
478 writel_relaxed(rate->pdiv * PLL4502_LOCK_FACTOR, pll->lock_reg); in samsung_pll45xx_set_rate()
481 writel_relaxed(rate->pdiv * PLL4508_LOCK_FACTOR, pll->lock_reg); in samsung_pll45xx_set_rate()
488 writel_relaxed(con1, pll->con_reg + 0x4); in samsung_pll45xx_set_rate()
489 writel_relaxed(con0, pll->con_reg); in samsung_pll45xx_set_rate()
493 while (!(readl_relaxed(pll->con_reg) & PLL45XX_LOCKED)) { in samsung_pll45xx_set_rate()
498 __func__, clk_hw_get_name(hw)); in samsung_pll45xx_set_rate()
499 return -EFAULT; in samsung_pll45xx_set_rate()
547 static unsigned long samsung_pll46xx_recalc_rate(struct clk_hw *hw, in samsung_pll46xx_recalc_rate() argument
550 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll46xx_recalc_rate()
554 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll46xx_recalc_rate()
555 pll_con1 = readl_relaxed(pll->con_reg + 4); in samsung_pll46xx_recalc_rate()
556 mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & ((pll->type == pll_1460x) ? in samsung_pll46xx_recalc_rate()
560 kdiv = pll->type == pll_4650c ? pll_con1 & PLL4650C_KDIV_MASK : in samsung_pll46xx_recalc_rate()
563 shift = ((pll->type == pll_4600) || (pll->type == pll_1460x)) ? 16 : 10; in samsung_pll46xx_recalc_rate()
581 return (old_mdiv != rate->mdiv || old_pdiv != rate->pdiv in samsung_pll46xx_mpk_change()
582 || old_kdiv != rate->kdiv); in samsung_pll46xx_mpk_change()
585 static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate, in samsung_pll46xx_set_rate() argument
588 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll46xx_set_rate()
597 drate, clk_hw_get_name(hw)); in samsung_pll46xx_set_rate()
598 return -EINVAL; in samsung_pll46xx_set_rate()
601 con0 = readl_relaxed(pll->con_reg); in samsung_pll46xx_set_rate()
602 con1 = readl_relaxed(pll->con_reg + 0x4); in samsung_pll46xx_set_rate()
607 con0 |= rate->sdiv << PLL46XX_SDIV_SHIFT; in samsung_pll46xx_set_rate()
608 writel_relaxed(con0, pll->con_reg); in samsung_pll46xx_set_rate()
613 /* Set PLL lock time. */ in samsung_pll46xx_set_rate()
614 lock = rate->pdiv * PLL46XX_LOCK_FACTOR; in samsung_pll46xx_set_rate()
616 /* Maximum lock time bitfield is 16-bit. */ in samsung_pll46xx_set_rate()
620 if (pll->type == pll_1460x) { in samsung_pll46xx_set_rate()
629 con0 |= rate->vsel << PLL46XX_VSEL_SHIFT; in samsung_pll46xx_set_rate()
632 con0 |= (rate->mdiv << PLL46XX_MDIV_SHIFT) | in samsung_pll46xx_set_rate()
633 (rate->pdiv << PLL46XX_PDIV_SHIFT) | in samsung_pll46xx_set_rate()
634 (rate->sdiv << PLL46XX_SDIV_SHIFT); in samsung_pll46xx_set_rate()
637 con1 = readl_relaxed(pll->con_reg + 0x4); in samsung_pll46xx_set_rate()
641 con1 |= (rate->kdiv << PLL46XX_KDIV_SHIFT) | in samsung_pll46xx_set_rate()
642 (rate->mfr << PLL46XX_MFR_SHIFT) | in samsung_pll46xx_set_rate()
643 (rate->mrr << PLL46XX_MRR_SHIFT); in samsung_pll46xx_set_rate()
646 writel_relaxed(lock, pll->lock_reg); in samsung_pll46xx_set_rate()
647 writel_relaxed(con0, pll->con_reg); in samsung_pll46xx_set_rate()
648 writel_relaxed(con1, pll->con_reg + 0x4); in samsung_pll46xx_set_rate()
652 while (!(readl_relaxed(pll->con_reg) & PLL46XX_LOCKED)) { in samsung_pll46xx_set_rate()
657 __func__, clk_hw_get_name(hw)); in samsung_pll46xx_set_rate()
658 return -EFAULT; in samsung_pll46xx_set_rate()
690 static unsigned long samsung_pll6552_recalc_rate(struct clk_hw *hw, in samsung_pll6552_recalc_rate() argument
693 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll6552_recalc_rate()
697 pll_con = readl_relaxed(pll->con_reg); in samsung_pll6552_recalc_rate()
698 if (pll->type == pll_6552_s3c2416) { in samsung_pll6552_recalc_rate()
730 static unsigned long samsung_pll6553_recalc_rate(struct clk_hw *hw, in samsung_pll6553_recalc_rate() argument
733 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll6553_recalc_rate()
737 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll6553_recalc_rate()
738 pll_con1 = readl_relaxed(pll->con_reg + 0x4); in samsung_pll6553_recalc_rate()
768 static unsigned long samsung_s3c2410_pll_recalc_rate(struct clk_hw *hw, in samsung_s3c2410_pll_recalc_rate() argument
771 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_s3c2410_pll_recalc_rate()
775 pll_con = readl_relaxed(pll->con_reg); in samsung_s3c2410_pll_recalc_rate()
786 static unsigned long samsung_s3c2440_mpll_recalc_rate(struct clk_hw *hw, in samsung_s3c2440_mpll_recalc_rate() argument
789 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_s3c2440_mpll_recalc_rate()
793 pll_con = readl_relaxed(pll->con_reg); in samsung_s3c2440_mpll_recalc_rate()
804 static int samsung_s3c2410_pll_set_rate(struct clk_hw *hw, unsigned long drate, in samsung_s3c2410_pll_set_rate() argument
807 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_s3c2410_pll_set_rate()
815 drate, clk_hw_get_name(hw)); in samsung_s3c2410_pll_set_rate()
816 return -EINVAL; in samsung_s3c2410_pll_set_rate()
819 tmp = readl_relaxed(pll->con_reg); in samsung_s3c2410_pll_set_rate()
825 tmp |= (rate->mdiv << PLLS3C2410_MDIV_SHIFT) | in samsung_s3c2410_pll_set_rate()
826 (rate->pdiv << PLLS3C2410_PDIV_SHIFT) | in samsung_s3c2410_pll_set_rate()
827 (rate->sdiv << PLLS3C2410_SDIV_SHIFT); in samsung_s3c2410_pll_set_rate()
828 writel_relaxed(tmp, pll->con_reg); in samsung_s3c2410_pll_set_rate()
830 /* Time to settle according to the manual */ in samsung_s3c2410_pll_set_rate()
836 static int samsung_s3c2410_pll_enable(struct clk_hw *hw, int bit, bool enable) in samsung_s3c2410_pll_enable() argument
838 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_s3c2410_pll_enable()
839 u32 pll_en = readl_relaxed(pll->lock_reg + PLLS3C2410_ENABLE_REG_OFFSET); in samsung_s3c2410_pll_enable()
847 writel_relaxed(pll_en, pll->lock_reg + PLLS3C2410_ENABLE_REG_OFFSET); in samsung_s3c2410_pll_enable()
849 /* if we started the UPLL, then allow to settle */ in samsung_s3c2410_pll_enable()
856 static int samsung_s3c2410_mpll_enable(struct clk_hw *hw) in samsung_s3c2410_mpll_enable() argument
858 return samsung_s3c2410_pll_enable(hw, 5, true); in samsung_s3c2410_mpll_enable()
861 static void samsung_s3c2410_mpll_disable(struct clk_hw *hw) in samsung_s3c2410_mpll_disable() argument
863 samsung_s3c2410_pll_enable(hw, 5, false); in samsung_s3c2410_mpll_disable()
866 static int samsung_s3c2410_upll_enable(struct clk_hw *hw) in samsung_s3c2410_upll_enable() argument
868 return samsung_s3c2410_pll_enable(hw, 7, true); in samsung_s3c2410_upll_enable()
871 static void samsung_s3c2410_upll_disable(struct clk_hw *hw) in samsung_s3c2410_upll_disable() argument
873 samsung_s3c2410_pll_enable(hw, 7, false); in samsung_s3c2410_upll_disable()
931 static unsigned long samsung_pll2550x_recalc_rate(struct clk_hw *hw, in samsung_pll2550x_recalc_rate() argument
934 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2550x_recalc_rate()
938 pll_stat = readl_relaxed(pll->con_reg); in samsung_pll2550x_recalc_rate()
960 /* Maximum lock time can be 270 * PDIV cycles */
972 static unsigned long samsung_pll2550xx_recalc_rate(struct clk_hw *hw, in samsung_pll2550xx_recalc_rate() argument
975 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2550xx_recalc_rate()
979 pll_con = readl_relaxed(pll->con_reg); in samsung_pll2550xx_recalc_rate()
1000 static int samsung_pll2550xx_set_rate(struct clk_hw *hw, unsigned long drate, in samsung_pll2550xx_set_rate() argument
1003 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2550xx_set_rate()
1011 drate, clk_hw_get_name(hw)); in samsung_pll2550xx_set_rate()
1012 return -EINVAL; in samsung_pll2550xx_set_rate()
1015 tmp = readl_relaxed(pll->con_reg); in samsung_pll2550xx_set_rate()
1017 if (!(samsung_pll2550xx_mp_change(rate->mdiv, rate->pdiv, tmp))) { in samsung_pll2550xx_set_rate()
1020 tmp |= rate->sdiv << PLL2550XX_S_SHIFT; in samsung_pll2550xx_set_rate()
1021 writel_relaxed(tmp, pll->con_reg); in samsung_pll2550xx_set_rate()
1026 /* Set PLL lock time. */ in samsung_pll2550xx_set_rate()
1027 writel_relaxed(rate->pdiv * PLL2550XX_LOCK_FACTOR, pll->lock_reg); in samsung_pll2550xx_set_rate()
1033 tmp |= (rate->mdiv << PLL2550XX_M_SHIFT) | in samsung_pll2550xx_set_rate()
1034 (rate->pdiv << PLL2550XX_P_SHIFT) | in samsung_pll2550xx_set_rate()
1035 (rate->sdiv << PLL2550XX_S_SHIFT); in samsung_pll2550xx_set_rate()
1036 writel_relaxed(tmp, pll->con_reg); in samsung_pll2550xx_set_rate()
1041 tmp = readl_relaxed(pll->con_reg); in samsung_pll2550xx_set_rate()
1062 /* Maximum lock time can be 3000 * PDIV cycles */
1077 static unsigned long samsung_pll2650x_recalc_rate(struct clk_hw *hw, in samsung_pll2650x_recalc_rate() argument
1080 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2650x_recalc_rate()
1085 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll2650x_recalc_rate()
1090 pll_con1 = readl_relaxed(pll->con_reg + 4); in samsung_pll2650x_recalc_rate()
1100 static int samsung_pll2650x_set_rate(struct clk_hw *hw, unsigned long drate, in samsung_pll2650x_set_rate() argument
1103 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2650x_set_rate()
1111 drate, clk_hw_get_name(hw)); in samsung_pll2650x_set_rate()
1112 return -EINVAL; in samsung_pll2650x_set_rate()
1115 con0 = readl_relaxed(pll->con_reg); in samsung_pll2650x_set_rate()
1116 con1 = readl_relaxed(pll->con_reg + 4); in samsung_pll2650x_set_rate()
1118 /* Set PLL lock time. */ in samsung_pll2650x_set_rate()
1119 writel_relaxed(rate->pdiv * PLL2650X_LOCK_FACTOR, pll->lock_reg); in samsung_pll2650x_set_rate()
1125 con0 |= (rate->mdiv << PLL2650X_M_SHIFT) | in samsung_pll2650x_set_rate()
1126 (rate->pdiv << PLL2650X_P_SHIFT) | in samsung_pll2650x_set_rate()
1127 (rate->sdiv << PLL2650X_S_SHIFT); in samsung_pll2650x_set_rate()
1129 writel_relaxed(con0, pll->con_reg); in samsung_pll2650x_set_rate()
1132 con1 |= ((rate->kdiv & PLL2650X_K_MASK) << PLL2650X_K_SHIFT); in samsung_pll2650x_set_rate()
1133 writel_relaxed(con1, pll->con_reg + 4); in samsung_pll2650x_set_rate()
1137 con0 = readl_relaxed(pll->con_reg); in samsung_pll2650x_set_rate()
1158 /* Maximum lock time can be 3000 * PDIV cycles */
1173 static unsigned long samsung_pll2650xx_recalc_rate(struct clk_hw *hw, in samsung_pll2650xx_recalc_rate() argument
1176 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2650xx_recalc_rate()
1181 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll2650xx_recalc_rate()
1182 pll_con2 = readl_relaxed(pll->con_reg + 8); in samsung_pll2650xx_recalc_rate()
1195 static int samsung_pll2650xx_set_rate(struct clk_hw *hw, unsigned long drate, in samsung_pll2650xx_set_rate() argument
1198 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2650xx_set_rate()
1205 drate, clk_hw_get_name(hw)); in samsung_pll2650xx_set_rate()
1206 return -EINVAL; in samsung_pll2650xx_set_rate()
1209 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll2650xx_set_rate()
1210 pll_con2 = readl_relaxed(pll->con_reg + 8); in samsung_pll2650xx_set_rate()
1216 pll_con0 |= rate->mdiv << PLL2650XX_MDIV_SHIFT; in samsung_pll2650xx_set_rate()
1217 pll_con0 |= rate->pdiv << PLL2650XX_PDIV_SHIFT; in samsung_pll2650xx_set_rate()
1218 pll_con0 |= rate->sdiv << PLL2650XX_SDIV_SHIFT; in samsung_pll2650xx_set_rate()
1223 pll_con2 |= ((~(rate->kdiv) + 1) & PLL2650XX_KDIV_MASK) in samsung_pll2650xx_set_rate()
1226 /* Set PLL lock time. */ in samsung_pll2650xx_set_rate()
1227 writel_relaxed(PLL2650XX_LOCK_FACTOR * rate->pdiv, pll->lock_reg); in samsung_pll2650xx_set_rate()
1229 writel_relaxed(pll_con0, pll->con_reg); in samsung_pll2650xx_set_rate()
1230 writel_relaxed(pll_con2, pll->con_reg + 8); in samsung_pll2650xx_set_rate()
1233 tmp = readl_relaxed(pll->con_reg); in samsung_pll2650xx_set_rate()
1260 __func__, pll_clk->name); in _samsung_clk_register_pll()
1264 init.name = pll_clk->name; in _samsung_clk_register_pll()
1265 init.flags = pll_clk->flags; in _samsung_clk_register_pll()
1266 init.parent_names = &pll_clk->parent_name; in _samsung_clk_register_pll()
1269 if (pll_clk->rate_table) { in _samsung_clk_register_pll()
1271 for (len = 0; pll_clk->rate_table[len].rate != 0; ) in _samsung_clk_register_pll()
1274 pll->rate_count = len; in _samsung_clk_register_pll()
1275 pll->rate_table = kmemdup(pll_clk->rate_table, in _samsung_clk_register_pll()
1276 pll->rate_count * in _samsung_clk_register_pll()
1279 WARN(!pll->rate_table, in _samsung_clk_register_pll()
1281 __func__, pll_clk->name); in _samsung_clk_register_pll()
1284 switch (pll_clk->type) { in _samsung_clk_register_pll()
1297 pll->enable_offs = PLL35XX_ENABLE_SHIFT; in _samsung_clk_register_pll()
1298 pll->lock_offs = PLL35XX_LOCK_STAT_SHIFT; in _samsung_clk_register_pll()
1299 if (!pll->rate_table) in _samsung_clk_register_pll()
1309 if (!pll->rate_table) in _samsung_clk_register_pll()
1317 pll->enable_offs = PLL36XX_ENABLE_SHIFT; in _samsung_clk_register_pll()
1318 pll->lock_offs = PLL36XX_LOCK_STAT_SHIFT; in _samsung_clk_register_pll()
1319 if (!pll->rate_table) in _samsung_clk_register_pll()
1335 if (!pll->rate_table) in _samsung_clk_register_pll()
1341 if (!pll->rate_table) in _samsung_clk_register_pll()
1347 if (!pll->rate_table) in _samsung_clk_register_pll()
1353 if (!pll->rate_table) in _samsung_clk_register_pll()
1362 if (!pll->rate_table) in _samsung_clk_register_pll()
1368 if (!pll->rate_table) in _samsung_clk_register_pll()
1374 if (!pll->rate_table) in _samsung_clk_register_pll()
1381 __func__, pll_clk->name); in _samsung_clk_register_pll()
1384 pll->hw.init = &init; in _samsung_clk_register_pll()
1385 pll->type = pll_clk->type; in _samsung_clk_register_pll()
1386 pll->lock_reg = base + pll_clk->lock_offset; in _samsung_clk_register_pll()
1387 pll->con_reg = base + pll_clk->con_offset; in _samsung_clk_register_pll()
1389 ret = clk_hw_register(ctx->dev, &pll->hw); in _samsung_clk_register_pll()
1392 __func__, pll_clk->name, ret); in _samsung_clk_register_pll()
1397 samsung_clk_add_lookup(ctx, &pll->hw, pll_clk->id); in _samsung_clk_register_pll()