Lines Matching +full:1 +full:mhz
92 #define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)
93 #define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
94 #define PWR_CTRL1_USE_CORE3_WFE (1 << 7)
95 #define PWR_CTRL1_USE_CORE2_WFE (1 << 6)
96 #define PWR_CTRL1_USE_CORE1_WFE (1 << 5)
97 #define PWR_CTRL1_USE_CORE0_WFE (1 << 4)
98 #define PWR_CTRL1_USE_CORE3_WFI (1 << 3)
99 #define PWR_CTRL1_USE_CORE2_WFI (1 << 2)
100 #define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
101 #define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
227 FFACTOR(0, "sclk_mpll_1600", "mout_mpll", 1, 1, 0),
228 FFACTOR(0, "sclk_mpll_mif", "mout_mpll", 1, 2, 0),
229 FFACTOR(0, "sclk_bpll", "fout_bpll", 1, 2, 0),
230 FFACTOR(0, "div_cam_blk_320", "sclk_mpll_1600", 1, 5, 0),
231 FFACTOR(0, "div_lcd_blk_145", "sclk_mpll_1600", 1, 11, 0),
234 FFACTOR(CLK_FIN_PLL, "fin_pll", "xusbxti", 1, 1, 0),
248 SRC_LEFTBUS, 4, 1),
249 MUX(CLK_MOUT_GDL, "mout_gdl", mout_gdl_p, SRC_LEFTBUS, 0, 1),
253 SRC_RIGHTBUS, 4, 1),
254 MUX(CLK_MOUT_GDR, "mout_gdr", mout_gdr_p, SRC_RIGHTBUS, 0, 1),
257 MUX(CLK_MOUT_EBI, "mout_ebi", mout_ebi_p, SRC_TOP0, 28, 1),
258 MUX(CLK_MOUT_ACLK_200, "mout_aclk_200", group_div_mpll_pre_p,SRC_TOP0, 24, 1),
259 MUX(CLK_MOUT_ACLK_160, "mout_aclk_160", group_div_mpll_pre_p, SRC_TOP0, 20, 1),
260 MUX(CLK_MOUT_ACLK_100, "mout_aclk_100", group_div_mpll_pre_p, SRC_TOP0, 16, 1),
261 MUX(CLK_MOUT_ACLK_266_1, "mout_aclk_266_1", mout_aclk_266_1_p, SRC_TOP0, 14, 1),
262 MUX(CLK_MOUT_ACLK_266_0, "mout_aclk_266_0", mout_aclk_266_0_p, SRC_TOP0, 13, 1),
263 MUX(CLK_MOUT_ACLK_266, "mout_aclk_266", mout_aclk_266_p, SRC_TOP0, 12, 1),
264 MUX(CLK_MOUT_VPLL, "mout_vpll", mout_vpll_p, SRC_TOP0, 8, 1),
265 MUX(CLK_MOUT_EPLL_USER, "mout_epll_user", mout_epll_user_p, SRC_TOP0, 4, 1),
266 MUX(CLK_MOUT_EBI_1, "mout_ebi_1", mout_ebi_1_p, SRC_TOP0, 0, 1),
269 MUX(CLK_MOUT_UPLL, "mout_upll", mout_upll_p, SRC_TOP1, 28, 1),
271 SRC_TOP1, 24, 1),
272 MUX(CLK_MOUT_ACLK_266_SUB, "mout_aclk_266_sub", mout_aclk_266_sub_p, SRC_TOP1, 20, 1),
273 MUX(CLK_MOUT_MPLL, "mout_mpll", mout_mpll_p, SRC_TOP1, 12, 1),
274 MUX(CLK_MOUT_ACLK_400_MCUISP, "mout_aclk_400_mcuisp", group_div_mpll_pre_p, SRC_TOP1, 8, 1),
275 MUX(CLK_MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
282 MUX(CLK_MOUT_MFC, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
283 MUX(CLK_MOUT_MFC_1, "mout_mfc_1", group_epll_vpll_p, SRC_MFC, 4, 1),
284 MUX(CLK_MOUT_MFC_0, "mout_mfc_0", group_div_mpll_pre_p, SRC_MFC, 0, 1),
287 MUX(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1),
288 MUX(CLK_MOUT_G3D_1, "mout_g3d_1", group_epll_vpll_p, SRC_G3D, 4, 1),
289 MUX(CLK_MOUT_G3D_0, "mout_g3d_0", group_div_mpll_pre_p, SRC_G3D, 0, 1),
318 SRC_CPU, 24, 1),
319 MUX(CLK_MOUT_HPM, "mout_hpm", mout_hpm_p, SRC_CPU, 20, 1),
320 MUX_F(CLK_MOUT_CORE, "mout_core", mout_core_p, SRC_CPU, 16, 1,
322 MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
443 GATE(CLK_PPMULEFT, "ppmuleft", "div_aclk_100", GATE_IP_LEFTBUS, 1,
457 GATE(CLK_PPMURIGHT, "ppmuright", "div_aclk_100", GATE_IP_RIGHTBUS, 1,
499 GATE(CLK_SYSREG, "sysreg", "div_aclk_100", GATE_IP_PERIR, 1,
510 GATE_SCLK_CAM, 1, CLK_SET_RATE_PARENT, 0),
538 GATE_SCLK_ISP_TOP, 1, CLK_SET_RATE_PARENT, 0),
549 GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
566 GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
596 GATE(CLK_GSCALER1, "gscaler1", "div_cam_blk_320", GATE_IP_CAM, 1, 0, 0),
604 GATE(CLK_SMMUMFC_L, "smmumfc_l", "div_aclk_200", GATE_IP_MFC, 1, 0, 0),
611 GATE(CLK_PPMUG3D, "ppmug3d", "div_aclk_200", GATE_IP_G3D, 1,
634 GATE_IP_ISP, 1, 0, 0),
646 GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
664 GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
670 PLL_35XX_RATE(24 * MHZ, 1200000000, 400, 4, 1),
671 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
672 PLL_35XX_RATE(24 * MHZ, 1066000000, 533, 6, 1),
673 PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1),
674 PLL_35XX_RATE(24 * MHZ, 960000000, 320, 4, 1),
675 PLL_35XX_RATE(24 * MHZ, 900000000, 300, 4, 1),
676 PLL_35XX_RATE(24 * MHZ, 850000000, 425, 6, 1),
677 PLL_35XX_RATE(24 * MHZ, 800000000, 200, 3, 1),
678 PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1),
679 PLL_35XX_RATE(24 * MHZ, 667000000, 667, 12, 1),
680 PLL_35XX_RATE(24 * MHZ, 600000000, 400, 4, 2),
681 PLL_35XX_RATE(24 * MHZ, 533000000, 533, 6, 2),
682 PLL_35XX_RATE(24 * MHZ, 520000000, 260, 3, 2),
683 PLL_35XX_RATE(24 * MHZ, 500000000, 250, 3, 2),
684 PLL_35XX_RATE(24 * MHZ, 400000000, 200, 3, 2),
685 PLL_35XX_RATE(24 * MHZ, 200000000, 200, 3, 3),
686 PLL_35XX_RATE(24 * MHZ, 100000000, 200, 3, 4),
692 PLL_36XX_RATE(24 * MHZ, 800000000, 200, 3, 1, 0),
693 PLL_36XX_RATE(24 * MHZ, 288000000, 96, 2, 2, 0),
694 PLL_36XX_RATE(24 * MHZ, 192000000, 128, 2, 3, 0),
695 PLL_36XX_RATE(24 * MHZ, 144000000, 96, 2, 3, 0),
696 PLL_36XX_RATE(24 * MHZ, 96000000, 128, 2, 4, 0),
697 PLL_36XX_RATE(24 * MHZ, 84000000, 112, 2, 4, 0),
698 PLL_36XX_RATE(24 * MHZ, 80000003, 106, 2, 4, 43691),
699 PLL_36XX_RATE(24 * MHZ, 73728000, 98, 2, 4, 19923),
700 PLL_36XX_RATE(24 * MHZ, 67737598, 270, 3, 5, 62285),
701 PLL_36XX_RATE(24 * MHZ, 65535999, 174, 2, 5, 49982),
702 PLL_36XX_RATE(24 * MHZ, 50000000, 200, 3, 5, 0),
703 PLL_36XX_RATE(24 * MHZ, 49152002, 131, 2, 5, 4719),
704 PLL_36XX_RATE(24 * MHZ, 48000000, 128, 2, 5, 0),
705 PLL_36XX_RATE(24 * MHZ, 45158401, 180, 3, 5, 41524),
711 PLL_36XX_RATE(24 * MHZ, 600000000, 100, 2, 1, 0),
712 PLL_36XX_RATE(24 * MHZ, 533000000, 266, 3, 2, 32768),
713 PLL_36XX_RATE(24 * MHZ, 519230987, 173, 2, 2, 5046),
714 PLL_36XX_RATE(24 * MHZ, 500000000, 250, 3, 2, 0),
715 PLL_36XX_RATE(24 * MHZ, 445500000, 148, 2, 2, 32768),
716 PLL_36XX_RATE(24 * MHZ, 445055007, 148, 2, 2, 23047),
717 PLL_36XX_RATE(24 * MHZ, 400000000, 200, 3, 2, 0),
718 PLL_36XX_RATE(24 * MHZ, 371250000, 123, 2, 2, 49152),
719 PLL_36XX_RATE(24 * MHZ, 370878997, 185, 3, 2, 28803),
720 PLL_36XX_RATE(24 * MHZ, 340000000, 170, 3, 2, 0),
721 PLL_36XX_RATE(24 * MHZ, 335000015, 111, 2, 2, 43691),
722 PLL_36XX_RATE(24 * MHZ, 333000000, 111, 2, 2, 0),
723 PLL_36XX_RATE(24 * MHZ, 330000000, 110, 2, 2, 0),
724 PLL_36XX_RATE(24 * MHZ, 320000015, 106, 2, 2, 43691),
725 PLL_36XX_RATE(24 * MHZ, 300000000, 100, 2, 2, 0),
726 PLL_36XX_RATE(24 * MHZ, 275000000, 275, 3, 3, 0),
727 PLL_36XX_RATE(24 * MHZ, 222750000, 148, 2, 3, 32768),
728 PLL_36XX_RATE(24 * MHZ, 222528007, 148, 2, 3, 23069),
729 PLL_36XX_RATE(24 * MHZ, 160000000, 160, 3, 3, 0),
730 PLL_36XX_RATE(24 * MHZ, 148500000, 99, 2, 3, 0),
731 PLL_36XX_RATE(24 * MHZ, 148352005, 98, 2, 3, 59070),
732 PLL_36XX_RATE(24 * MHZ, 108000000, 144, 2, 4, 0),
733 PLL_36XX_RATE(24 * MHZ, 74250000, 99, 2, 4, 0),
734 PLL_36XX_RATE(24 * MHZ, 74176002, 98, 2, 4, 59070),
735 PLL_36XX_RATE(24 * MHZ, 54054000, 216, 3, 5, 14156),
736 PLL_36XX_RATE(24 * MHZ, 54000000, 144, 2, 5, 0),
795 { 1000000, E3250_CPU_DIV0(1, 7, 4, 1), E3250_CPU_DIV1(7, 7), },
796 { 900000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
797 { 800000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
798 { 700000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
799 { 600000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
800 { 500000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
801 { 400000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
802 { 300000, E3250_CPU_DIV0(1, 5, 3, 1), E3250_CPU_DIV1(7, 7), },
803 { 200000, E3250_CPU_DIV0(1, 3, 3, 1), E3250_CPU_DIV1(7, 7), },
804 { 100000, E3250_CPU_DIV0(1, 1, 1, 1), E3250_CPU_DIV1(7, 7), },
886 MUX(CLK_MOUT_MPLL_MIF, "mout_mpll_mif", mout_mpll_mif_p, SRC_DMC, 12, 1),
887 MUX(CLK_MOUT_BPLL, "mout_bpll", mout_bpll_p, SRC_DMC, 10, 1),
888 MUX(CLK_MOUT_DPHY, "mout_dphy", mout_dphy_p, SRC_DMC, 8, 1),
889 MUX(CLK_MOUT_DMC_BUS, "mout_dmc_bus", mout_dphy_p, SRC_DMC, 4, 1),
892 MUX(CLK_MOUT_EPLL, "mout_epll", mout_epll_p, SRC_EPLL, 4, 1),
1032 GATE_IP_ISP0, 1, CLK_IGNORE_UNUSED, 0),