140 	unsigned long div0;  in exynos_set_safe_div()  local
142 	div0 = readl(base + E4210_DIV_CPU0);  in exynos_set_safe_div()
143 	div0 = (div0 & ~mask) | (div & mask);  in exynos_set_safe_div()
144 	writel(div0, base + E4210_DIV_CPU0);  in exynos_set_safe_div()
155 	unsigned long div0, div1 = 0, mux_reg;  in exynos_cpuclk_pre_rate_change()  local
172 	div0 = cfg_data->div0;  in exynos_cpuclk_pre_rate_change()
203 		div0 |= alt_div;  in exynos_cpuclk_pre_rate_change()
212 	writel(div0, base + E4210_DIV_CPU0);  in exynos_cpuclk_pre_rate_change()
251 		div |= (cfg_data->div0 & E4210_DIV0_ATB_MASK);  in exynos_cpuclk_post_rate_change()
268 	unsigned long div0;  in exynos5433_set_safe_div()  local
270 	div0 = readl(base + E5433_DIV_CPU0);  in exynos5433_set_safe_div()
271 	div0 = (div0 & ~mask) | (div & mask);  in exynos5433_set_safe_div()
272 	writel(div0, base + E5433_DIV_CPU0);  in exynos5433_set_safe_div()
283 	unsigned long div0, div1 = 0, mux_reg;  in exynos5433_cpuclk_pre_rate_change()  local
299 	div0 = cfg_data->div0;  in exynos5433_cpuclk_pre_rate_change()
317 		div0 |= alt_div;  in exynos5433_cpuclk_pre_rate_change()
326 	writel(div0, base + E5433_DIV_CPU0);  in exynos5433_cpuclk_pre_rate_change()