Lines Matching +full:core +full:- +full:module

1 /* SPDX-License-Identifier: GPL-2.0 */
3  * Renesas Clock Pulse Generator / Module Standby and Software Reset
12      * Definitions of CPG Core Clocks
15      *   - Clock outputs exported to DT
16      *   - External input clocks
17      *   - Internal CPG clocks
26 	unsigned int parent;	/* Core Clocks only */
61      * Definitions of Module Clocks
67 	unsigned int parent;	/* Add MOD_CLK_BASE for Module Clocks */
70 /* Convert from sparse base-100 to packed index space */
71 #define MOD_CLK_PACK(x)	((x) - ((x) / 100) * (100 - 32))
78 /* Convert from sparse base-10 to packed index space */
95      * SoC-specific CPG/MSSR Description
97      * @early_core_clks: Array of Early Core Clock definitions
99      * @early_mod_clks: Array of Early Module Clock definitions
102      * @core_clks: Array of Core Clock definitions
104      * @last_dt_core_clk: ID of the last Core Clock exported to DT
105      * @num_total_core_clks: Total number of Core Clocks (exported + internal)
107      * @mod_clks: Array of Module Clock definitions
109      * @num_hw_mod_clks: Number of Module Clocks supported by the hardware
111      * @crit_mod_clks: Array with Module Clock IDs of critical clocks that
116      * @core_pm_clks: Array with IDs of Core Clocks that are suitable for Power
117      *                Management, in addition to Module Clocks
120      * @init: Optional callback to perform SoC-specific initialization
121      * @cpg_clk_register: Optional callback to handle special Core Clock types
131 	/* Core Clocks */
138 	/* Module Clocks */
143 	/* Critical Module Clocks that should not be disabled */
147 	/* Core Clocks suitable for PM, in addition to the Module Clocks */
154 					const struct cpg_core_clk *core,