1 // SPDX-License-Identifier: GPL-2.0
3  * r8a7790 Common Clock Framework support
10 #include <linux/clk-provider.h>
20 #include "clk-div6.h"
27  * struct div6_clock - CPG 6 bit divider clock
28  * @hw: handle between common and hardware-specific interfaces
29  * @reg: IO-remapped register
30  * @div: divisor value (1-64)
31  * @src_shift: Shift to access the register bits to select the parent clock
32  * @src_width: Number of register bits to select the parent clock (may be 0)
33  * @nb: Notifier block to save/restore clock state for system resume
50 	struct div6_clock *clock = to_div6_clock(hw);  in cpg_div6_clock_enable()  local
53 	val = (readl(clock->reg) & ~(CPG_DIV6_DIV_MASK | CPG_DIV6_CKSTP))  in cpg_div6_clock_enable()
54 	    | CPG_DIV6_DIV(clock->div - 1);  in cpg_div6_clock_enable()
55 	writel(val, clock->reg);  in cpg_div6_clock_enable()
62 	struct div6_clock *clock = to_div6_clock(hw);  in cpg_div6_clock_disable()  local
65 	val = readl(clock->reg);  in cpg_div6_clock_disable()
68 	 * DIV6 clocks require the divisor field to be non-zero when stopping  in cpg_div6_clock_disable()
69 	 * the clock. However, some clocks (e.g. ZB on sh73a0) fail to be  in cpg_div6_clock_disable()
70 	 * re-enabled later if the divisor field is changed when stopping the  in cpg_div6_clock_disable()
71 	 * clock  in cpg_div6_clock_disable()
75 	writel(val, clock->reg);  in cpg_div6_clock_disable()
80 	struct div6_clock *clock = to_div6_clock(hw);  in cpg_div6_clock_is_enabled()  local
82 	return !(readl(clock->reg) & CPG_DIV6_CKSTP);  in cpg_div6_clock_is_enabled()
88 	struct div6_clock *clock = to_div6_clock(hw);  in cpg_div6_clock_recalc_rate()  local
90 	return parent_rate / clock->div;  in cpg_div6_clock_recalc_rate()
116 	struct div6_clock *clock = to_div6_clock(hw);  in cpg_div6_clock_set_rate()  local
120 	clock->div = div;  in cpg_div6_clock_set_rate()
122 	val = readl(clock->reg) & ~CPG_DIV6_DIV_MASK;  in cpg_div6_clock_set_rate()
123 	/* Only program the new divisor if the clock isn't stopped. */  in cpg_div6_clock_set_rate()
125 		writel(val | CPG_DIV6_DIV(clock->div - 1), clock->reg);  in cpg_div6_clock_set_rate()
132 	struct div6_clock *clock = to_div6_clock(hw);  in cpg_div6_clock_get_parent()  local
136 	if (clock->src_width == 0)  in cpg_div6_clock_get_parent()
139 	hw_index = (readl(clock->reg) >> clock->src_shift) &  in cpg_div6_clock_get_parent()
140 		   (BIT(clock->src_width) - 1);  in cpg_div6_clock_get_parent()
142 		if (clock->parents[i] == hw_index)  in cpg_div6_clock_get_parent()
146 	pr_err("%s: %s DIV6 clock set to invalid parent %u\n",  in cpg_div6_clock_get_parent()
153 	struct div6_clock *clock = to_div6_clock(hw);  in cpg_div6_clock_set_parent()  local
158 		return -EINVAL;  in cpg_div6_clock_set_parent()
160 	mask = ~((BIT(clock->src_width) - 1) << clock->src_shift);  in cpg_div6_clock_set_parent()
161 	hw_index = clock->parents[index];  in cpg_div6_clock_set_parent()
163 	writel((readl(clock->reg) & mask) | (hw_index << clock->src_shift),  in cpg_div6_clock_set_parent()
164 	       clock->reg);  in cpg_div6_clock_set_parent()
183 	struct div6_clock *clock = container_of(nb, struct div6_clock, nb);  in cpg_div6_clock_notifier_call()  local
191 		 * R/SH-Mobile SoCs, while the resume functionality is only  in cpg_div6_clock_notifier_call()
192 		 * needed on R-Car Gen3.  in cpg_div6_clock_notifier_call()
194 		if (__clk_get_enable_count(clock->hw.clk))  in cpg_div6_clock_notifier_call()
195 			cpg_div6_clock_enable(&clock->hw);  in cpg_div6_clock_notifier_call()
197 			cpg_div6_clock_disable(&clock->hw);  in cpg_div6_clock_notifier_call()
205  * cpg_div6_register - Register a DIV6 clock
206  * @name: Name of the DIV6 clock
207  * @num_parents: Number of parent clocks of the DIV6 clock (1, 4, or 8)
209  * @reg: Mapped register used to control the DIV6 clock
212 struct clk * __init cpg_div6_register(const char *name,  in cpg_div6_register()  argument
220 	struct div6_clock *clock;  in cpg_div6_register()  local
224 	clock = kzalloc(struct_size(clock, parents, num_parents), GFP_KERNEL);  in cpg_div6_register()
225 	if (!clock)  in cpg_div6_register()
226 		return ERR_PTR(-ENOMEM);  in cpg_div6_register()
228 	clock->reg = reg;  in cpg_div6_register()
231 	 * Read the divisor. Disabling the clock overwrites the divisor, so we  in cpg_div6_register()
234 	clock->div = (readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1;  in cpg_div6_register()
238 		/* fixed parent clock */  in cpg_div6_register()
239 		clock->src_shift = clock->src_width = 0;  in cpg_div6_register()
242 		/* clock with EXSRC bits 6-7 */  in cpg_div6_register()
243 		clock->src_shift = 6;  in cpg_div6_register()
244 		clock->src_width = 2;  in cpg_div6_register()
247 		/* VCLK with EXSRC bits 12-14 */  in cpg_div6_register()
248 		clock->src_shift = 12;  in cpg_div6_register()
249 		clock->src_width = 3;  in cpg_div6_register()
252 		pr_err("%s: invalid number of parents for DIV6 clock %s\n",  in cpg_div6_register()
253 		       __func__, name);  in cpg_div6_register()
254 		clk = ERR_PTR(-EINVAL);  in cpg_div6_register()
262 			clock->parents[valid_parents] = i;  in cpg_div6_register()
267 	/* Register the clock. */  in cpg_div6_register()
268 	init.name = name;  in cpg_div6_register()
274 	clock->hw.init = &init;  in cpg_div6_register()
276 	clk = clk_register(NULL, &clock->hw);  in cpg_div6_register()
281 		clock->nb.notifier_call = cpg_div6_clock_notifier_call;  in cpg_div6_register()
282 		raw_notifier_chain_register(notifiers, &clock->nb);  in cpg_div6_register()
288 	kfree(clock);  in cpg_div6_register()
296 	const char *clk_name = np->name;  in cpg_div6_clock_init()
303 		pr_err("%s: no parent found for %pOFn DIV6 clock\n",  in cpg_div6_clock_init()
315 		pr_err("%s: failed to map %pOFn DIV6 clock register\n",  in cpg_div6_clock_init()
321 	of_property_read_string(np, "clock-output-names", &clk_name);  in cpg_div6_clock_init()
328 		pr_err("%s: failed to register %pOFn DIV6 clock (%ld)\n",  in cpg_div6_clock_init()
343 CLK_OF_DECLARE(cpg_div6_clk, "renesas,cpg-div6-clock", cpg_div6_clock_init);