Lines Matching +full:0 +full:x104c
65 { 0x0, 1 },
66 { 0x1, 2 },
67 { 0x3, 4 },
68 { 0x7, 8 },
73 .offset = 0xc000,
76 .enable_reg = 0x1e0,
77 .enable_mask = BIT(0),
91 .offset = 0xc000,
106 .offset = 0xc050,
109 .enable_reg = 0x1e0,
124 .offset = 0xc050,
139 .offset = 0x0,
153 .offset = 0x0,
168 .offset = 0x50,
182 .offset = 0x50,
197 .offset = 0xa0,
211 .offset = 0xa0,
226 .offset = 0xf0,
240 .offset = 0xf0,
255 .offset = 0x140,
269 .offset = 0x140,
284 .offset = 0x190,
298 .offset = 0x190,
313 { P_XO, 0 },
325 { P_XO, 0 },
339 { P_XO, 0 },
353 { P_XO, 0 },
367 { P_XO, 0 },
381 { P_XO, 0 },
397 { P_XO, 0 },
415 { P_XO, 0 },
433 { P_XO, 0 },
453 { P_XO, 0 },
473 { P_XO, 0 },
493 { P_XO, 0 },
515 .cmd_rcgr = 0x2120,
528 .cmd_rcgr = 0x2140,
541 F(37500000, P_GPLL0, 16, 0, 0),
542 F(50000000, P_GPLL0, 12, 0, 0),
543 F(100000000, P_GPLL0, 6, 0, 0),
548 .cmd_rcgr = 0x3300,
561 F(100000000, P_GPLL0, 6, 0, 0),
562 F(200000000, P_GPLL0, 3, 0, 0),
563 F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
564 F(404000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
565 F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
566 F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
567 F(600000000, P_GPLL0, 1, 0, 0),
572 .cmd_rcgr = 0x3640,
585 F(164571429, P_MMPLL10_OUT_EVEN, 3.5, 0, 0),
586 F(256000000, P_MMPLL4_OUT_EVEN, 3, 0, 0),
587 F(274290000, P_MMPLL7_OUT_EVEN, 3.5, 0, 0),
588 F(300000000, P_GPLL0, 2, 0, 0),
589 F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
590 F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
595 .cmd_rcgr = 0x3090,
608 .cmd_rcgr = 0x3100,
621 .cmd_rcgr = 0x3160,
634 .cmd_rcgr = 0x31c0,
647 F(164571429, P_MMPLL10_OUT_EVEN, 3.5, 0, 0),
648 F(256000000, P_MMPLL4_OUT_EVEN, 3, 0, 0),
649 F(274290000, P_MMPLL7_OUT_EVEN, 3.5, 0, 0),
650 F(300000000, P_GPLL0, 2, 0, 0),
651 F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
656 .cmd_rcgr = 0x3800,
669 F(200000000, P_GPLL0, 3, 0, 0),
670 F(269333333, P_MMPLL0_OUT_EVEN, 3, 0, 0),
675 .cmd_rcgr = 0x3000,
688 .cmd_rcgr = 0x3030,
701 .cmd_rcgr = 0x3060,
714 F(19200000, P_XO, 1, 0, 0),
719 .cmd_rcgr = 0x2260,
739 .cmd_rcgr = 0x2220,
752 F(162000, P_DPLINK, 2, 0, 0),
753 F(270000, P_DPLINK, 2, 0, 0),
754 F(540000, P_DPLINK, 2, 0, 0),
759 .cmd_rcgr = 0x2200,
772 F(154000000, P_DPVCO, 1, 0, 0),
773 F(337500000, P_DPVCO, 2, 0, 0),
774 F(675000000, P_DPVCO, 2, 0, 0),
779 .cmd_rcgr = 0x2240,
792 F(19200000, P_XO, 1, 0, 0),
797 .cmd_rcgr = 0x2160,
810 .cmd_rcgr = 0x2180,
828 .cmd_rcgr = 0x2060,
842 F(100000000, P_GPLL0, 6, 0, 0),
843 F(200000000, P_GPLL0, 3, 0, 0),
844 F(404000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
845 F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
846 F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
851 .cmd_rcgr = 0x3b00,
864 F(19200000, P_XO, 1, 0, 0),
869 .cmd_rcgr = 0x2100,
882 F(75000000, P_GPLL0, 8, 0, 0),
883 F(150000000, P_GPLL0, 4, 0, 0),
884 F(320000000, P_MMPLL7_OUT_EVEN, 3, 0, 0),
885 F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
890 .cmd_rcgr = 0x3500,
903 F(19200000, P_XO, 1, 0, 0),
904 F(75000000, P_GPLL0_DIV, 4, 0, 0),
905 F(171428571, P_GPLL0, 3.5, 0, 0),
906 F(323200000, P_MMPLL0_OUT_EVEN, 2.5, 0, 0),
907 F(406000000, P_MMPLL1_OUT_EVEN, 2, 0, 0),
912 .cmd_rcgr = 0xf020,
925 F(4800000, P_XO, 4, 0, 0),
928 F(9600000, P_XO, 2, 0, 0),
930 F(19200000, P_XO, 1, 0, 0),
939 .cmd_rcgr = 0x3360,
952 .cmd_rcgr = 0x3390,
965 .cmd_rcgr = 0x33c0,
978 .cmd_rcgr = 0x33f0,
991 F(85714286, P_GPLL0, 7, 0, 0),
992 F(100000000, P_GPLL0, 6, 0, 0),
993 F(150000000, P_GPLL0, 4, 0, 0),
994 F(171428571, P_GPLL0, 3.5, 0, 0),
995 F(200000000, P_GPLL0, 3, 0, 0),
996 F(275000000, P_MMPLL5_OUT_EVEN, 3, 0, 0),
997 F(300000000, P_GPLL0, 2, 0, 0),
998 F(330000000, P_MMPLL5_OUT_EVEN, 2.5, 0, 0),
999 F(412500000, P_MMPLL5_OUT_EVEN, 2, 0, 0),
1004 .cmd_rcgr = 0x2040,
1017 F(19200000, P_XO, 1, 0, 0),
1022 .cmd_rcgr = 0x2080,
1035 F(19200000, P_XO, 1, 0, 0),
1036 F(40000000, P_GPLL0, 15, 0, 0),
1037 F(80800000, P_MMPLL0_OUT_EVEN, 10, 0, 0),
1042 .cmd_rcgr = 0x5000,
1055 F(75000000, P_GPLL0, 8, 0, 0),
1056 F(171428571, P_GPLL0, 3.5, 0, 0),
1057 F(240000000, P_GPLL0, 2.5, 0, 0),
1058 F(323200000, P_MMPLL0_OUT_EVEN, 2.5, 0, 0),
1059 F(406000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
1065 .cmd_rcgr = 0xd000,
1078 .cmd_rcgr = 0x2000,
1092 .cmd_rcgr = 0x2020,
1106 F(171428571, P_GPLL0, 3.5, 0, 0),
1107 F(275000000, P_MMPLL5_OUT_EVEN, 3, 0, 0),
1108 F(330000000, P_MMPLL5_OUT_EVEN, 2.5, 0, 0),
1109 F(412500000, P_MMPLL5_OUT_EVEN, 2, 0, 0),
1114 .cmd_rcgr = 0x21a0,
1127 F(200000000, P_GPLL0, 3, 0, 0),
1128 F(269330000, P_MMPLL0_OUT_EVEN, 3, 0, 0),
1129 F(355200000, P_MMPLL6_OUT_EVEN, 2.5, 0, 0),
1130 F(444000000, P_MMPLL6_OUT_EVEN, 2, 0, 0),
1131 F(533000000, P_MMPLL3_OUT_EVEN, 2, 0, 0),
1136 .cmd_rcgr = 0x1000,
1149 .cmd_rcgr = 0x1060,
1162 .cmd_rcgr = 0x1080,
1175 F(200000000, P_GPLL0, 3, 0, 0),
1176 F(300000000, P_GPLL0, 2, 0, 0),
1177 F(320000000, P_MMPLL7_OUT_EVEN, 3, 0, 0),
1178 F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
1179 F(404000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
1180 F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
1181 F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
1182 F(600000000, P_GPLL0, 1, 0, 0),
1187 .cmd_rcgr = 0x3600,
1200 .cmd_rcgr = 0x3620,
1213 .halt_reg = 0x328,
1215 .enable_reg = 0x328,
1216 .enable_mask = BIT(0),
1228 .halt_reg = 0x1028,
1230 .enable_reg = 0x1028,
1231 .enable_mask = BIT(0),
1243 .halt_reg = 0x1030,
1245 .enable_reg = 0x1030,
1246 .enable_mask = BIT(0),
1258 .halt_reg = 0x1034,
1260 .enable_reg = 0x1034,
1261 .enable_mask = BIT(0),
1272 .halt_reg = 0x1038,
1274 .enable_reg = 0x1038,
1275 .enable_mask = BIT(0),
1287 .halt_reg = 0x1048,
1289 .enable_reg = 0x1048,
1290 .enable_mask = BIT(0),
1302 .halt_reg = 0x104c,
1304 .enable_reg = 0x104c,
1305 .enable_mask = BIT(0),
1317 .halt_reg = 0x2308,
1319 .enable_reg = 0x2308,
1320 .enable_mask = BIT(0),
1332 .halt_reg = 0x230c,
1334 .enable_reg = 0x230c,
1335 .enable_mask = BIT(0),
1347 .halt_reg = 0x2310,
1349 .enable_reg = 0x2310,
1350 .enable_mask = BIT(0),
1361 .halt_reg = 0x2314,
1363 .enable_reg = 0x2314,
1364 .enable_mask = BIT(0),
1376 .halt_reg = 0x2318,
1378 .enable_reg = 0x2318,
1379 .enable_mask = BIT(0),
1391 .halt_reg = 0x231c,
1393 .enable_reg = 0x231c,
1394 .enable_mask = BIT(0),
1406 .halt_reg = 0x2320,
1408 .enable_reg = 0x2320,
1409 .enable_mask = BIT(0),
1421 .halt_reg = 0x2324,
1423 .enable_reg = 0x2324,
1424 .enable_mask = BIT(0),
1436 .halt_reg = 0x2328,
1438 .enable_reg = 0x2328,
1439 .enable_mask = BIT(0),
1451 .halt_reg = 0x2338,
1453 .enable_reg = 0x2338,
1454 .enable_mask = BIT(0),
1466 .halt_reg = 0x233c,
1468 .enable_reg = 0x233c,
1469 .enable_mask = BIT(0),
1481 .halt_reg = 0x2340,
1483 .enable_reg = 0x2340,
1484 .enable_mask = BIT(0),
1496 .halt_reg = 0x2344,
1498 .enable_reg = 0x2344,
1499 .enable_mask = BIT(0),
1511 .halt_reg = 0x2348,
1513 .enable_reg = 0x2348,
1514 .enable_mask = BIT(0),
1526 .halt_reg = 0x2350,
1528 .enable_reg = 0x2350,
1529 .enable_mask = BIT(0),
1541 .halt_reg = 0x2354,
1543 .enable_reg = 0x2354,
1544 .enable_mask = BIT(0),
1556 .halt_reg = 0x2358,
1558 .enable_reg = 0x2358,
1559 .enable_mask = BIT(0),
1571 .halt_reg = 0x235c,
1573 .enable_reg = 0x235c,
1574 .enable_mask = BIT(0),
1586 .halt_reg = 0x2360,
1588 .enable_reg = 0x2360,
1589 .enable_mask = BIT(0),
1601 .halt_reg = 0x2364,
1603 .enable_reg = 0x2364,
1604 .enable_mask = BIT(0),
1616 .halt_reg = 0x2374,
1618 .enable_reg = 0x2374,
1619 .enable_mask = BIT(0),
1631 .halt_reg = 0x2378,
1633 .enable_reg = 0x2378,
1634 .enable_mask = BIT(0),
1646 .halt_reg = 0x3024,
1648 .enable_reg = 0x3024,
1649 .enable_mask = BIT(0),
1661 .halt_reg = 0x3054,
1663 .enable_reg = 0x3054,
1664 .enable_mask = BIT(0),
1676 .halt_reg = 0x3084,
1678 .enable_reg = 0x3084,
1679 .enable_mask = BIT(0),
1691 .halt_reg = 0x30b4,
1693 .enable_reg = 0x30b4,
1694 .enable_mask = BIT(0),
1706 .halt_reg = 0x30bc,
1708 .enable_reg = 0x30bc,
1709 .enable_mask = BIT(0),
1721 .halt_reg = 0x30d4,
1723 .enable_reg = 0x30d4,
1724 .enable_mask = BIT(0),
1736 .halt_reg = 0x30e4,
1738 .enable_reg = 0x30e4,
1739 .enable_mask = BIT(0),
1751 .halt_reg = 0x3124,
1753 .enable_reg = 0x3124,
1754 .enable_mask = BIT(0),
1766 .halt_reg = 0x3128,
1768 .enable_reg = 0x3128,
1769 .enable_mask = BIT(0),
1781 .halt_reg = 0x3144,
1783 .enable_reg = 0x3144,
1784 .enable_mask = BIT(0),
1796 .halt_reg = 0x3154,
1798 .enable_reg = 0x3154,
1799 .enable_mask = BIT(0),
1811 .halt_reg = 0x3184,
1813 .enable_reg = 0x3184,
1814 .enable_mask = BIT(0),
1826 .halt_reg = 0x3188,
1828 .enable_reg = 0x3188,
1829 .enable_mask = BIT(0),
1841 .halt_reg = 0x31a4,
1843 .enable_reg = 0x31a4,
1844 .enable_mask = BIT(0),
1856 .halt_reg = 0x31b4,
1858 .enable_reg = 0x31b4,
1859 .enable_mask = BIT(0),
1871 .halt_reg = 0x31e4,
1873 .enable_reg = 0x31e4,
1874 .enable_mask = BIT(0),
1886 .halt_reg = 0x31e8,
1888 .enable_reg = 0x31e8,
1889 .enable_mask = BIT(0),
1901 .halt_reg = 0x3204,
1903 .enable_reg = 0x3204,
1904 .enable_mask = BIT(0),
1916 .halt_reg = 0x3214,
1918 .enable_reg = 0x3214,
1919 .enable_mask = BIT(0),
1931 .halt_reg = 0x3224,
1933 .enable_reg = 0x3224,
1934 .enable_mask = BIT(0),
1946 .halt_reg = 0x3344,
1948 .enable_reg = 0x3344,
1949 .enable_mask = BIT(0),
1961 .halt_reg = 0x3348,
1963 .enable_reg = 0x3348,
1964 .enable_mask = BIT(0),
1976 .halt_reg = 0x3384,
1978 .enable_reg = 0x3384,
1979 .enable_mask = BIT(0),
1991 .halt_reg = 0x33b4,
1993 .enable_reg = 0x33b4,
1994 .enable_mask = BIT(0),
2006 .halt_reg = 0x33e4,
2008 .enable_reg = 0x33e4,
2009 .enable_mask = BIT(0),
2021 .halt_reg = 0x3414,
2023 .enable_reg = 0x3414,
2024 .enable_mask = BIT(0),
2036 .halt_reg = 0x3484,
2038 .enable_reg = 0x3484,
2039 .enable_mask = BIT(0),
2051 .halt_reg = 0x348c,
2053 .enable_reg = 0x348c,
2054 .enable_mask = BIT(0),
2066 .halt_reg = 0x3494,
2068 .enable_reg = 0x3494,
2069 .enable_mask = BIT(0),
2081 .halt_reg = 0x35a8,
2083 .enable_reg = 0x35a8,
2084 .enable_mask = BIT(0),
2096 .halt_reg = 0x35b4,
2098 .enable_reg = 0x35b4,
2099 .enable_mask = BIT(0),
2111 .halt_reg = 0x35b8,
2113 .enable_reg = 0x35b8,
2114 .enable_mask = BIT(0),
2125 .halt_reg = 0x3668,
2127 .enable_reg = 0x3668,
2128 .enable_mask = BIT(0),
2140 .halt_reg = 0x3678,
2142 .enable_reg = 0x3678,
2143 .enable_mask = BIT(0),
2155 .halt_reg = 0x36a8,
2157 .enable_reg = 0x36a8,
2158 .enable_mask = BIT(0),
2170 .halt_reg = 0x36ac,
2172 .enable_reg = 0x36ac,
2173 .enable_mask = BIT(0),
2185 .halt_reg = 0x36b0,
2187 .enable_reg = 0x36b0,
2188 .enable_mask = BIT(0),
2200 .halt_reg = 0x36b4,
2202 .enable_reg = 0x36b4,
2203 .enable_mask = BIT(0),
2215 .halt_reg = 0x36b8,
2217 .enable_reg = 0x36b8,
2218 .enable_mask = BIT(0),
2230 .halt_reg = 0x36bc,
2232 .enable_reg = 0x36bc,
2233 .enable_mask = BIT(0),
2244 .halt_reg = 0x36c4,
2246 .enable_reg = 0x36c4,
2247 .enable_mask = BIT(0),
2258 .halt_reg = 0x36c8,
2260 .enable_reg = 0x36c8,
2261 .enable_mask = BIT(0),
2273 .halt_reg = 0x3704,
2275 .enable_reg = 0x3704,
2276 .enable_mask = BIT(0),
2288 .halt_reg = 0x3714,
2290 .enable_reg = 0x3714,
2291 .enable_mask = BIT(0),
2303 .halt_reg = 0x3720,
2305 .enable_reg = 0x3720,
2306 .enable_mask = BIT(0),
2318 .halt_reg = 0x3724,
2320 .enable_reg = 0x3724,
2321 .enable_mask = BIT(0),
2333 .halt_reg = 0x3730,
2335 .enable_reg = 0x3730,
2336 .enable_mask = BIT(0),
2348 .halt_reg = 0x3734,
2350 .enable_reg = 0x3734,
2351 .enable_mask = BIT(0),
2363 .halt_reg = 0x3738,
2365 .enable_reg = 0x3738,
2366 .enable_mask = BIT(0),
2378 .halt_reg = 0x373c,
2380 .enable_reg = 0x373c,
2381 .enable_mask = BIT(0),
2393 .halt_reg = 0x3740,
2395 .enable_reg = 0x3740,
2396 .enable_mask = BIT(0),
2408 .halt_reg = 0x3744,
2410 .enable_reg = 0x3744,
2411 .enable_mask = BIT(0),
2423 .halt_reg = 0x3748,
2425 .enable_reg = 0x3748,
2426 .enable_mask = BIT(0),
2438 .halt_reg = 0x3b68,
2440 .enable_reg = 0x3b68,
2441 .enable_mask = BIT(0),
2453 .halt_reg = 0x3b6c,
2455 .enable_reg = 0x3b6c,
2456 .enable_mask = BIT(0),
2468 .halt_reg = 0x3b74,
2470 .enable_reg = 0x3b74,
2471 .enable_mask = BIT(0),
2483 .halt_reg = 0x5024,
2485 .enable_reg = 0x5024,
2486 .enable_mask = BIT(0),
2498 .halt_reg = 0xe004,
2500 .enable_reg = 0xe004,
2501 .enable_mask = BIT(0),
2513 .halt_reg = 0xe008,
2515 .enable_reg = 0xe008,
2516 .enable_mask = BIT(0),
2527 .halt_reg = 0xf004,
2529 .enable_reg = 0xf004,
2530 .enable_mask = BIT(0),
2542 .halt_reg = 0xf064,
2544 .enable_reg = 0xf064,
2545 .enable_mask = BIT(0),
2557 .halt_reg = 0xf068,
2559 .enable_reg = 0xf068,
2560 .enable_mask = BIT(0),
2576 .gdscr = 0x1024,
2584 .gdscr = 0x1040,
2593 .gdscr = 0x1044,
2602 .gdscr = 0x2304,
2603 .cxcs = (unsigned int []){ 0x2310, 0x2350, 0x231c, 0x2320 },
2612 .gdscr = 0x34a0,
2613 .cxcs = (unsigned int []){ 0x35b8, 0x36c4, 0x3704, 0x3714, 0x3494,
2614 0x35a8, 0x3868 },
2623 .gdscr = 0x3664,
2632 .gdscr = 0x3674,
2641 .gdscr = 0x36d4,
2650 .gdscr = 0xe020,
2651 .gds_hw_ctrl = 0xe024,
2821 [SPDM_BCR] = { 0x200 },
2822 [SPDM_RM_BCR] = { 0x300 },
2823 [MISC_BCR] = { 0x320 },
2824 [VIDEO_TOP_BCR] = { 0x1020 },
2825 [THROTTLE_VIDEO_BCR] = { 0x1180 },
2826 [MDSS_BCR] = { 0x2300 },
2827 [THROTTLE_MDSS_BCR] = { 0x2460 },
2828 [CAMSS_PHY0_BCR] = { 0x3020 },
2829 [CAMSS_PHY1_BCR] = { 0x3050 },
2830 [CAMSS_PHY2_BCR] = { 0x3080 },
2831 [CAMSS_CSI0_BCR] = { 0x30b0 },
2832 [CAMSS_CSI0RDI_BCR] = { 0x30d0 },
2833 [CAMSS_CSI0PIX_BCR] = { 0x30e0 },
2834 [CAMSS_CSI1_BCR] = { 0x3120 },
2835 [CAMSS_CSI1RDI_BCR] = { 0x3140 },
2836 [CAMSS_CSI1PIX_BCR] = { 0x3150 },
2837 [CAMSS_CSI2_BCR] = { 0x3180 },
2838 [CAMSS_CSI2RDI_BCR] = { 0x31a0 },
2839 [CAMSS_CSI2PIX_BCR] = { 0x31b0 },
2840 [CAMSS_CSI3_BCR] = { 0x31e0 },
2841 [CAMSS_CSI3RDI_BCR] = { 0x3200 },
2842 [CAMSS_CSI3PIX_BCR] = { 0x3210 },
2843 [CAMSS_ISPIF_BCR] = { 0x3220 },
2844 [CAMSS_CCI_BCR] = { 0x3340 },
2845 [CAMSS_TOP_BCR] = { 0x3480 },
2846 [CAMSS_AHB_BCR] = { 0x3488 },
2847 [CAMSS_MICRO_BCR] = { 0x3490 },
2848 [CAMSS_JPEG_BCR] = { 0x35a0 },
2849 [CAMSS_VFE0_BCR] = { 0x3660 },
2850 [CAMSS_VFE1_BCR] = { 0x3670 },
2851 [CAMSS_VFE_VBIF_BCR] = { 0x36a0 },
2852 [CAMSS_CPP_TOP_BCR] = { 0x36c0 },
2853 [CAMSS_CPP_BCR] = { 0x36d0 },
2854 [CAMSS_CSI_VFE0_BCR] = { 0x3700 },
2855 [CAMSS_CSI_VFE1_BCR] = { 0x3710 },
2856 [CAMSS_FD_BCR] = { 0x3b60 },
2857 [THROTTLE_CAMSS_BCR] = { 0x3c30 },
2858 [MNOCAHB_BCR] = { 0x5020 },
2859 [MNOCAXI_BCR] = { 0xd020 },
2860 [BMIC_SMMU_BCR] = { 0xe000 },
2861 [MNOC_MAXI_BCR] = { 0xf000 },
2862 [VMEM_BCR] = { 0xf060 },
2863 [BTO_BCR] = { 0x10004 },
2870 .max_register = 0x10004,