Lines Matching +full:0 +full:x104c
49 { P_XO, 0 },
59 { P_XO, 0 },
71 { P_XO, 0 },
83 { P_XO, 0 },
95 { P_XO, 0 },
109 { P_XO, 0 },
125 { P_XO, 0 },
141 { P_XO, 0 },
157 { P_XO, 0 },
173 { P_XO, 0 },
191 { P_XO, 0 },
211 { P_XO, 0 },
245 { 1500000000, 2000000000, 0 },
251 { 1500000000, 2000000000, 0 },
255 { 500000000, 1500000000, 0 },
259 .offset = 0x0,
264 .enable_reg = 0x100,
265 .enable_mask = BIT(0),
276 .offset = 0x0,
289 .offset = 0x30,
294 .enable_reg = 0x100,
306 .offset = 0x30,
319 .offset = 0x4100,
332 .offset = 0x4100,
345 .offset = 0x60,
358 .offset = 0x60,
371 .offset = 0x90,
384 .offset = 0x90,
397 .offset = 0xc0,
410 .offset = 0xc0,
423 .offset = 0x4130,
436 .offset = 0x4130,
449 .offset = 0x4200,
462 .offset = 0x4200,
475 F(19200000, P_XO, 1, 0, 0),
476 F(40000000, P_GPLL0_DIV, 7.5, 0, 0),
477 F(80000000, P_MMPLL0, 10, 0, 0),
482 .cmd_rcgr = 0x5000,
495 F(19200000, P_XO, 1, 0, 0),
496 F(75000000, P_GPLL0_DIV, 4, 0, 0),
497 F(100000000, P_GPLL0, 6, 0, 0),
498 F(171430000, P_GPLL0, 3.5, 0, 0),
499 F(200000000, P_GPLL0, 3, 0, 0),
500 F(320000000, P_MMPLL0, 2.5, 0, 0),
501 F(400000000, P_MMPLL0, 2, 0, 0),
506 .cmd_rcgr = 0x5040,
519 .cmd_rcgr = 0x5090,
532 .cmd_rcgr = 0x4000,
545 F(19200000, P_XO, 1, 0, 0),
550 .cmd_rcgr = 0x4090,
563 .cmd_rcgr = 0x4010,
575 F(19200000, P_XO, 1, 0, 0),
576 F(50000000, P_GPLL0, 12, 0, 0),
581 .cmd_rcgr = 0x4060,
594 F(75000000, P_GPLL0_DIV, 4, 0, 0),
595 F(150000000, P_GPLL0, 4, 0, 0),
596 F(346666667, P_MMPLL3, 3, 0, 0),
597 F(520000000, P_MMPLL3, 2, 0, 0),
602 .cmd_rcgr = 0x1000,
616 .cmd_rcgr = 0x1060,
630 .cmd_rcgr = 0x1080,
644 .cmd_rcgr = 0x2000,
658 .cmd_rcgr = 0x2020,
672 F(85714286, P_GPLL0, 7, 0, 0),
673 F(100000000, P_GPLL0, 6, 0, 0),
674 F(150000000, P_GPLL0, 4, 0, 0),
675 F(171428571, P_GPLL0, 3.5, 0, 0),
676 F(200000000, P_GPLL0, 3, 0, 0),
677 F(275000000, P_MMPLL5, 3, 0, 0),
678 F(300000000, P_GPLL0, 2, 0, 0),
679 F(330000000, P_MMPLL5, 2.5, 0, 0),
680 F(412500000, P_MMPLL5, 2, 0, 0),
685 .cmd_rcgr = 0x2040,
703 .cmd_rcgr = 0x2060,
717 F(19200000, P_XO, 1, 0, 0),
722 .cmd_rcgr = 0x2080,
735 F(19200000, P_XO, 1, 0, 0),
740 .cmd_rcgr = 0x2100,
753 .cmd_rcgr = 0x2120,
766 .cmd_rcgr = 0x2140,
779 F(19200000, P_XO, 1, 0, 0),
784 .cmd_rcgr = 0x2160,
797 .cmd_rcgr = 0x2180,
820 .cmd_rcgr = 0x3420,
834 .cmd_rcgr = 0x3450,
848 F(4800000, P_XO, 4, 0, 0),
851 F(9600000, P_XO, 2, 0, 0),
853 F(19200000, P_XO, 1, 0, 0),
862 .cmd_rcgr = 0x3360,
876 .cmd_rcgr = 0x3390,
890 .cmd_rcgr = 0x33c0,
904 .cmd_rcgr = 0x33f0,
918 F(19200000, P_XO, 1, 0, 0),
919 F(37500000, P_GPLL0, 16, 0, 0),
920 F(50000000, P_GPLL0, 12, 0, 0),
921 F(100000000, P_GPLL0, 6, 0, 0),
926 .cmd_rcgr = 0x3300,
940 F(100000000, P_GPLL0_DIV, 3, 0, 0),
941 F(200000000, P_GPLL0, 3, 0, 0),
942 F(266666667, P_MMPLL0, 3, 0, 0),
947 .cmd_rcgr = 0x3000,
960 .cmd_rcgr = 0x3030,
973 .cmd_rcgr = 0x3060,
986 F(100000000, P_GPLL0_DIV, 3, 0, 0),
987 F(200000000, P_GPLL0, 3, 0, 0),
988 F(320000000, P_MMPLL4, 3, 0, 0),
989 F(384000000, P_MMPLL4, 2.5, 0, 0),
994 .cmd_rcgr = 0x3240,
1007 .cmd_rcgr = 0x3260,
1020 .cmd_rcgr = 0x3280,
1033 F(75000000, P_GPLL0_DIV, 4, 0, 0),
1034 F(150000000, P_GPLL0, 4, 0, 0),
1035 F(228571429, P_MMPLL0, 3.5, 0, 0),
1036 F(266666667, P_MMPLL0, 3, 0, 0),
1037 F(320000000, P_MMPLL0, 2.5, 0, 0),
1038 F(480000000, P_MMPLL4, 2, 0, 0),
1043 .cmd_rcgr = 0x3500,
1056 F(75000000, P_GPLL0_DIV, 4, 0, 0),
1057 F(150000000, P_GPLL0, 4, 0, 0),
1058 F(228571429, P_MMPLL0, 3.5, 0, 0),
1059 F(266666667, P_MMPLL0, 3, 0, 0),
1060 F(320000000, P_MMPLL0, 2.5, 0, 0),
1065 .cmd_rcgr = 0x3540,
1078 .cmd_rcgr = 0x3560,
1091 F(75000000, P_GPLL0_DIV, 4, 0, 0),
1092 F(100000000, P_GPLL0_DIV, 3, 0, 0),
1093 F(300000000, P_GPLL0, 2, 0, 0),
1094 F(320000000, P_MMPLL0, 2.5, 0, 0),
1095 F(480000000, P_MMPLL4, 2, 0, 0),
1096 F(600000000, P_GPLL0, 1, 0, 0),
1101 .cmd_rcgr = 0x3600,
1114 .cmd_rcgr = 0x3620,
1127 F(100000000, P_GPLL0_DIV, 3, 0, 0),
1128 F(200000000, P_GPLL0, 3, 0, 0),
1129 F(320000000, P_MMPLL0, 2.5, 0, 0),
1130 F(480000000, P_MMPLL4, 2, 0, 0),
1131 F(640000000, P_MMPLL4, 1.5, 0, 0),
1136 .cmd_rcgr = 0x3640,
1149 F(100000000, P_GPLL0_DIV, 3, 0, 0),
1150 F(200000000, P_GPLL0, 3, 0, 0),
1151 F(266666667, P_MMPLL0, 3, 0, 0),
1152 F(480000000, P_MMPLL4, 2, 0, 0),
1153 F(600000000, P_GPLL0, 1, 0, 0),
1158 .cmd_rcgr = 0x3090,
1171 .cmd_rcgr = 0x3100,
1184 .cmd_rcgr = 0x3160,
1197 .cmd_rcgr = 0x31c0,
1210 F(100000000, P_GPLL0_DIV, 3, 0, 0),
1211 F(200000000, P_GPLL0, 3, 0, 0),
1212 F(400000000, P_MMPLL0, 2, 0, 0),
1217 .cmd_rcgr = 0x3b00,
1230 .halt_reg = 0x5024,
1232 .enable_reg = 0x5024,
1233 .enable_mask = BIT(0),
1245 .halt_reg = 0x5054,
1247 .enable_reg = 0x5054,
1248 .enable_mask = BIT(0),
1260 .halt_reg = 0x5018,
1262 .enable_reg = 0x5018,
1263 .enable_mask = BIT(0),
1275 .halt_reg = 0x5014,
1277 .enable_reg = 0x5014,
1278 .enable_mask = BIT(0),
1289 .halt_reg = 0x5074,
1291 .enable_reg = 0x5074,
1292 .enable_mask = BIT(0),
1304 .halt_reg = 0x3c44,
1306 .enable_reg = 0x3c44,
1307 .enable_mask = BIT(0),
1319 .halt_reg = 0x3c48,
1321 .enable_reg = 0x3c48,
1322 .enable_mask = BIT(0),
1334 .halt_reg = 0x3c04,
1336 .enable_reg = 0x3c04,
1337 .enable_mask = BIT(0),
1349 .halt_reg = 0x3c08,
1351 .enable_reg = 0x3c08,
1352 .enable_mask = BIT(0),
1364 .halt_reg = 0x3c14,
1366 .enable_reg = 0x3c14,
1367 .enable_mask = BIT(0),
1379 .halt_reg = 0x3c18,
1381 .enable_reg = 0x3c18,
1382 .enable_mask = BIT(0),
1394 .halt_reg = 0x3c24,
1396 .enable_reg = 0x3c24,
1397 .enable_mask = BIT(0),
1409 .halt_reg = 0x3c28,
1411 .enable_reg = 0x3c28,
1412 .enable_mask = BIT(0),
1424 .halt_reg = 0x2474,
1426 .enable_reg = 0x2474,
1427 .enable_mask = BIT(0),
1439 .halt_reg = 0x2478,
1441 .enable_reg = 0x2478,
1442 .enable_mask = BIT(0),
1454 .halt_reg = 0x2444,
1456 .enable_reg = 0x2444,
1457 .enable_mask = BIT(0),
1469 .halt_reg = 0x2448,
1471 .enable_reg = 0x2448,
1472 .enable_mask = BIT(0),
1484 .halt_reg = 0x2454,
1486 .enable_reg = 0x2454,
1487 .enable_mask = BIT(0),
1499 .halt_reg = 0x2458,
1501 .enable_reg = 0x2458,
1502 .enable_mask = BIT(0),
1514 .halt_reg = 0x1194,
1516 .enable_reg = 0x1194,
1517 .enable_mask = BIT(0),
1529 .halt_reg = 0x1198,
1531 .enable_reg = 0x1198,
1532 .enable_mask = BIT(0),
1544 .halt_reg = 0x1174,
1546 .enable_reg = 0x1174,
1547 .enable_mask = BIT(0),
1559 .halt_reg = 0x1178,
1561 .enable_reg = 0x1178,
1562 .enable_mask = BIT(0),
1574 .halt_reg = 0x5298,
1576 .enable_reg = 0x5298,
1577 .enable_mask = BIT(0),
1589 .halt_reg = 0x4028,
1591 .enable_reg = 0x4028,
1592 .enable_mask = BIT(0),
1604 .halt_reg = 0x40b0,
1606 .enable_reg = 0x40b0,
1607 .enable_mask = BIT(0),
1619 .halt_reg = 0x403c,
1621 .enable_reg = 0x403c,
1622 .enable_mask = BIT(0),
1634 .halt_reg = 0x4044,
1636 .enable_reg = 0x4044,
1637 .enable_mask = BIT(0),
1649 .halt_reg = 0x1204,
1651 .enable_reg = 0x1204,
1652 .enable_mask = BIT(0),
1664 .halt_reg = 0x1208,
1666 .enable_reg = 0x1208,
1667 .enable_mask = BIT(0),
1679 .halt_reg = 0x4084,
1681 .enable_reg = 0x4084,
1682 .enable_mask = BIT(0),
1694 .halt_reg = 0x4088,
1696 .enable_reg = 0x4088,
1697 .enable_mask = BIT(0),
1709 .halt_reg = 0x1028,
1711 .enable_reg = 0x1028,
1712 .enable_mask = BIT(0),
1724 .halt_reg = 0x1034,
1726 .enable_reg = 0x1034,
1727 .enable_mask = BIT(0),
1739 .halt_reg = 0x1038,
1741 .enable_reg = 0x1038,
1742 .enable_mask = BIT(0),
1754 .halt_reg = 0x1030,
1756 .enable_reg = 0x1030,
1757 .enable_mask = BIT(0),
1769 .halt_reg = 0x1048,
1771 .enable_reg = 0x1048,
1772 .enable_mask = BIT(0),
1784 .halt_reg = 0x104c,
1786 .enable_reg = 0x104c,
1787 .enable_mask = BIT(0),
1799 .halt_reg = 0x2308,
1801 .enable_reg = 0x2308,
1802 .enable_mask = BIT(0),
1814 .halt_reg = 0x230c,
1816 .enable_reg = 0x230c,
1817 .enable_mask = BIT(0),
1829 .halt_reg = 0x2310,
1831 .enable_reg = 0x2310,
1832 .enable_mask = BIT(0),
1844 .halt_reg = 0x2314,
1846 .enable_reg = 0x2314,
1847 .enable_mask = BIT(0),
1859 .halt_reg = 0x2318,
1861 .enable_reg = 0x2318,
1862 .enable_mask = BIT(0),
1874 .halt_reg = 0x231c,
1876 .enable_reg = 0x231c,
1877 .enable_mask = BIT(0),
1889 .halt_reg = 0x2324,
1891 .enable_reg = 0x2324,
1892 .enable_mask = BIT(0),
1904 .halt_reg = 0x2328,
1906 .enable_reg = 0x2328,
1907 .enable_mask = BIT(0),
1919 .halt_reg = 0x2338,
1921 .enable_reg = 0x2338,
1922 .enable_mask = BIT(0),
1934 .halt_reg = 0x233c,
1936 .enable_reg = 0x233c,
1937 .enable_mask = BIT(0),
1949 .halt_reg = 0x2340,
1951 .enable_reg = 0x2340,
1952 .enable_mask = BIT(0),
1964 .halt_reg = 0x2344,
1966 .enable_reg = 0x2344,
1967 .enable_mask = BIT(0),
1979 .halt_reg = 0x2348,
1981 .enable_reg = 0x2348,
1982 .enable_mask = BIT(0),
1994 .halt_reg = 0x3484,
1996 .enable_reg = 0x3484,
1997 .enable_mask = BIT(0),
2009 .halt_reg = 0x348c,
2011 .enable_reg = 0x348c,
2012 .enable_mask = BIT(0),
2024 .halt_reg = 0x3494,
2026 .enable_reg = 0x3494,
2027 .enable_mask = BIT(0),
2039 .halt_reg = 0x3444,
2041 .enable_reg = 0x3444,
2042 .enable_mask = BIT(0),
2054 .halt_reg = 0x3474,
2056 .enable_reg = 0x3474,
2057 .enable_mask = BIT(0),
2069 .halt_reg = 0x3384,
2071 .enable_reg = 0x3384,
2072 .enable_mask = BIT(0),
2084 .halt_reg = 0x33b4,
2086 .enable_reg = 0x33b4,
2087 .enable_mask = BIT(0),
2099 .halt_reg = 0x33e4,
2101 .enable_reg = 0x33e4,
2102 .enable_mask = BIT(0),
2114 .halt_reg = 0x3414,
2116 .enable_reg = 0x3414,
2117 .enable_mask = BIT(0),
2129 .halt_reg = 0x3344,
2131 .enable_reg = 0x3344,
2132 .enable_mask = BIT(0),
2144 .halt_reg = 0x3348,
2146 .enable_reg = 0x3348,
2147 .enable_mask = BIT(0),
2159 .halt_reg = 0x3024,
2161 .enable_reg = 0x3024,
2162 .enable_mask = BIT(0),
2174 .halt_reg = 0x3054,
2176 .enable_reg = 0x3054,
2177 .enable_mask = BIT(0),
2189 .halt_reg = 0x3084,
2191 .enable_reg = 0x3084,
2192 .enable_mask = BIT(0),
2204 .halt_reg = 0x3234,
2206 .enable_reg = 0x3234,
2207 .enable_mask = BIT(0),
2219 .halt_reg = 0x3254,
2221 .enable_reg = 0x3254,
2222 .enable_mask = BIT(0),
2234 .halt_reg = 0x3274,
2236 .enable_reg = 0x3274,
2237 .enable_mask = BIT(0),
2249 .halt_reg = 0x35a8,
2251 .enable_reg = 0x35a8,
2252 .enable_mask = BIT(0),
2264 .halt_reg = 0x35b0,
2266 .enable_reg = 0x35b0,
2267 .enable_mask = BIT(0),
2279 .halt_reg = 0x35c0,
2281 .enable_reg = 0x35c0,
2282 .enable_mask = BIT(0),
2294 .halt_reg = 0x35b4,
2296 .enable_reg = 0x35b4,
2297 .enable_mask = BIT(0),
2309 .halt_reg = 0x35b8,
2311 .enable_reg = 0x35b8,
2312 .enable_mask = BIT(0),
2324 .halt_reg = 0x36b8,
2326 .enable_reg = 0x36b8,
2327 .enable_mask = BIT(0),
2339 .halt_reg = 0x36bc,
2341 .enable_reg = 0x36bc,
2342 .enable_mask = BIT(0),
2354 .halt_reg = 0x36a8,
2356 .enable_reg = 0x36a8,
2357 .enable_mask = BIT(0),
2369 .halt_reg = 0x3720,
2371 .enable_reg = 0x3720,
2372 .enable_mask = BIT(0),
2384 .halt_reg = 0x3668,
2386 .enable_reg = 0x3668,
2387 .enable_mask = BIT(0),
2399 .halt_reg = 0x36ac,
2401 .enable_reg = 0x36ac,
2402 .enable_mask = BIT(0),
2414 .halt_reg = 0x3724,
2416 .enable_reg = 0x3724,
2417 .enable_mask = BIT(0),
2429 .halt_reg = 0x3678,
2431 .enable_reg = 0x3678,
2432 .enable_mask = BIT(0),
2444 .halt_reg = 0x3704,
2446 .enable_reg = 0x3704,
2447 .enable_mask = BIT(0),
2459 .halt_reg = 0x3714,
2461 .enable_reg = 0x3714,
2462 .enable_mask = BIT(0),
2474 .halt_reg = 0x36c8,
2476 .enable_reg = 0x36c8,
2477 .enable_mask = BIT(0),
2489 .halt_reg = 0x36c4,
2491 .enable_reg = 0x36c4,
2492 .enable_mask = BIT(0),
2504 .halt_reg = 0x36b0,
2506 .enable_reg = 0x36b0,
2507 .enable_mask = BIT(0),
2519 .halt_reg = 0x36b4,
2521 .enable_reg = 0x36b4,
2522 .enable_mask = BIT(0),
2534 .halt_reg = 0x30b4,
2536 .enable_reg = 0x30b4,
2537 .enable_mask = BIT(0),
2549 .halt_reg = 0x30bc,
2551 .enable_reg = 0x30bc,
2552 .enable_mask = BIT(0),
2564 .halt_reg = 0x30c4,
2566 .enable_reg = 0x30c4,
2567 .enable_mask = BIT(0),
2579 .halt_reg = 0x30d4,
2581 .enable_reg = 0x30d4,
2582 .enable_mask = BIT(0),
2594 .halt_reg = 0x30e4,
2596 .enable_reg = 0x30e4,
2597 .enable_mask = BIT(0),
2609 .halt_reg = 0x3124,
2611 .enable_reg = 0x3124,
2612 .enable_mask = BIT(0),
2624 .halt_reg = 0x3128,
2626 .enable_reg = 0x3128,
2627 .enable_mask = BIT(0),
2639 .halt_reg = 0x3134,
2641 .enable_reg = 0x3134,
2642 .enable_mask = BIT(0),
2654 .halt_reg = 0x3144,
2656 .enable_reg = 0x3144,
2657 .enable_mask = BIT(0),
2669 .halt_reg = 0x3154,
2671 .enable_reg = 0x3154,
2672 .enable_mask = BIT(0),
2684 .halt_reg = 0x3184,
2686 .enable_reg = 0x3184,
2687 .enable_mask = BIT(0),
2699 .halt_reg = 0x3188,
2701 .enable_reg = 0x3188,
2702 .enable_mask = BIT(0),
2714 .halt_reg = 0x3194,
2716 .enable_reg = 0x3194,
2717 .enable_mask = BIT(0),
2729 .halt_reg = 0x31a4,
2731 .enable_reg = 0x31a4,
2732 .enable_mask = BIT(0),
2744 .halt_reg = 0x31b4,
2746 .enable_reg = 0x31b4,
2747 .enable_mask = BIT(0),
2759 .halt_reg = 0x31e4,
2761 .enable_reg = 0x31e4,
2762 .enable_mask = BIT(0),
2774 .halt_reg = 0x31e8,
2776 .enable_reg = 0x31e8,
2777 .enable_mask = BIT(0),
2789 .halt_reg = 0x31f4,
2791 .enable_reg = 0x31f4,
2792 .enable_mask = BIT(0),
2804 .halt_reg = 0x3204,
2806 .enable_reg = 0x3204,
2807 .enable_mask = BIT(0),
2819 .halt_reg = 0x3214,
2821 .enable_reg = 0x3214,
2822 .enable_mask = BIT(0),
2834 .halt_reg = 0x3224,
2836 .enable_reg = 0x3224,
2837 .enable_mask = BIT(0),
2849 .halt_reg = 0x3b68,
2851 .enable_reg = 0x3b68,
2852 .enable_mask = BIT(0),
2864 .halt_reg = 0x3b6c,
2866 .enable_reg = 0x3b6c,
2867 .enable_mask = BIT(0),
2879 .halt_reg = 0x3ba74,
2881 .enable_reg = 0x3ba74,
2882 .enable_mask = BIT(0),
2898 .gdscr = 0x529c,
2907 .gdscr = 0x119c,
2908 .gds_hw_ctrl = 0x120c,
2917 .gdscr = 0x247c,
2918 .gds_hw_ctrl = 0x2480,
2927 .gdscr = 0x3c4c,
2928 .gds_hw_ctrl = 0x3c50,
2937 .gdscr = 0x1024,
2938 .cxcs = (unsigned int []){ 0x1028, 0x1034, 0x1038 },
2948 .gdscr = 0x1040,
2949 .cxcs = (unsigned int []){ 0x1048 },
2960 .gdscr = 0x1044,
2961 .cxcs = (unsigned int []){ 0x104c },
2972 .gdscr = 0x34a0,
2973 .cxcs = (unsigned int []){ 0x36bc, 0x36c4 },
2983 .gdscr = 0x3664,
2984 .cxcs = (unsigned int []){ 0x36a8 },
2994 .gdscr = 0x3674,
2995 .cxcs = (unsigned int []){ 0x36ac },
3005 .gdscr = 0x35a4,
3006 .cxcs = (unsigned int []){ 0x35a8, 0x35b0, 0x35c0, 0x35b8 },
3016 .gdscr = 0x36d4,
3017 .cxcs = (unsigned int []){ 0x36b0 },
3027 .gdscr = 0x3b64,
3028 .cxcs = (unsigned int []){ 0x3b68, 0x3b6c },
3038 .gdscr = 0x2304,
3039 .cxcs = (unsigned int []){ 0x2310, 0x231c },
3049 .gdscr = 0x4034,
3050 .gds_hw_ctrl = 0x4038,
3059 .gdscr = 0x4024,
3060 .clamp_io_ctrl = 0x4300,
3061 .cxcs = (unsigned int []){ 0x4028 },
3266 [MMAGICAHB_BCR] = { 0x5020 },
3267 [MMAGIC_CFG_BCR] = { 0x5050 },
3268 [MISC_BCR] = { 0x5010 },
3269 [BTO_BCR] = { 0x5030 },
3270 [MMAGICAXI_BCR] = { 0x5060 },
3271 [MMAGICMAXI_BCR] = { 0x5070 },
3272 [DSA_BCR] = { 0x50a0 },
3273 [MMAGIC_CAMSS_BCR] = { 0x3c40 },
3274 [THROTTLE_CAMSS_BCR] = { 0x3c30 },
3275 [SMMU_VFE_BCR] = { 0x3c00 },
3276 [SMMU_CPP_BCR] = { 0x3c10 },
3277 [SMMU_JPEG_BCR] = { 0x3c20 },
3278 [MMAGIC_MDSS_BCR] = { 0x2470 },
3279 [THROTTLE_MDSS_BCR] = { 0x2460 },
3280 [SMMU_ROT_BCR] = { 0x2440 },
3281 [SMMU_MDP_BCR] = { 0x2450 },
3282 [MMAGIC_VIDEO_BCR] = { 0x1190 },
3283 [THROTTLE_VIDEO_BCR] = { 0x1180 },
3284 [SMMU_VIDEO_BCR] = { 0x1170 },
3285 [MMAGIC_BIMC_BCR] = { 0x5290 },
3286 [GPU_GX_BCR] = { 0x4020 },
3287 [GPU_BCR] = { 0x4030 },
3288 [GPU_AON_BCR] = { 0x4040 },
3289 [VMEM_BCR] = { 0x1200 },
3290 [MMSS_RBCPR_BCR] = { 0x4080 },
3291 [VIDEO_BCR] = { 0x1020 },
3292 [MDSS_BCR] = { 0x2300 },
3293 [CAMSS_TOP_BCR] = { 0x3480 },
3294 [CAMSS_AHB_BCR] = { 0x3488 },
3295 [CAMSS_MICRO_BCR] = { 0x3490 },
3296 [CAMSS_CCI_BCR] = { 0x3340 },
3297 [CAMSS_PHY0_BCR] = { 0x3020 },
3298 [CAMSS_PHY1_BCR] = { 0x3050 },
3299 [CAMSS_PHY2_BCR] = { 0x3080 },
3300 [CAMSS_CSIPHY0_3P_BCR] = { 0x3230 },
3301 [CAMSS_CSIPHY1_3P_BCR] = { 0x3250 },
3302 [CAMSS_CSIPHY2_3P_BCR] = { 0x3270 },
3303 [CAMSS_JPEG_BCR] = { 0x35a0 },
3304 [CAMSS_VFE_BCR] = { 0x36a0 },
3305 [CAMSS_VFE0_BCR] = { 0x3660 },
3306 [CAMSS_VFE1_BCR] = { 0x3670 },
3307 [CAMSS_CSI_VFE0_BCR] = { 0x3700 },
3308 [CAMSS_CSI_VFE1_BCR] = { 0x3710 },
3309 [CAMSS_CPP_TOP_BCR] = { 0x36c0 },
3310 [CAMSS_CPP_BCR] = { 0x36d0 },
3311 [CAMSS_CSI0_BCR] = { 0x30b0 },
3312 [CAMSS_CSI0RDI_BCR] = { 0x30d0 },
3313 [CAMSS_CSI0PIX_BCR] = { 0x30e0 },
3314 [CAMSS_CSI1_BCR] = { 0x3120 },
3315 [CAMSS_CSI1RDI_BCR] = { 0x3140 },
3316 [CAMSS_CSI1PIX_BCR] = { 0x3150 },
3317 [CAMSS_CSI2_BCR] = { 0x3180 },
3318 [CAMSS_CSI2RDI_BCR] = { 0x31a0 },
3319 [CAMSS_CSI2PIX_BCR] = { 0x31b0 },
3320 [CAMSS_CSI3_BCR] = { 0x31e0 },
3321 [CAMSS_CSI3RDI_BCR] = { 0x3200 },
3322 [CAMSS_CSI3PIX_BCR] = { 0x3210 },
3323 [CAMSS_ISPIF_BCR] = { 0x3220 },
3324 [FD_BCR] = { 0x3b60 },
3325 [MMSS_SPDM_RM_BCR] = { 0x300 },
3332 .max_register = 0xb008,
3363 regmap_update_bits(regmap, 0x50d8, BIT(31), 0); in mmcc_msm8996_probe()
3365 regmap_update_bits(regmap, 0x5054, BIT(15), 0); in mmcc_msm8996_probe()