Lines Matching +full:0 +full:x2c000
39 { P_XO, 0 },
53 { P_XO, 0 },
65 { P_XO, 0 },
81 { P_XO, 0 },
93 { P_XO, 0 },
107 { P_XO, 0 },
132 { 250000000, 2000000000, 0 },
137 .offset = 0x0,
142 .enable_reg = 0x52000,
143 .enable_mask = BIT(0),
154 .offset = 0x0,
165 .offset = 0x0,
176 .offset = 0x0,
187 .offset = 0x0,
198 .offset = 0x1000,
203 .enable_reg = 0x52000,
215 .offset = 0x1000,
226 .offset = 0x1000,
237 .offset = 0x1000,
248 .offset = 0x1000,
259 .offset = 0x2000,
264 .enable_reg = 0x52000,
276 .offset = 0x2000,
287 .offset = 0x2000,
298 .offset = 0x2000,
309 .offset = 0x2000,
320 .offset = 0x3000,
325 .enable_reg = 0x52000,
337 .offset = 0x3000,
348 .offset = 0x3000,
359 .offset = 0x3000,
370 .offset = 0x3000,
381 .offset = 0x77000,
386 .enable_reg = 0x52000,
398 .offset = 0x77000,
409 .offset = 0x77000,
420 .offset = 0x77000,
431 .offset = 0x77000,
442 F(19200000, P_XO, 1, 0, 0),
443 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
448 .cmd_rcgr = 0x19020,
449 .mnd_width = 0,
463 F(4800000, P_XO, 4, 0, 0),
464 F(9600000, P_XO, 2, 0, 0),
466 F(19200000, P_XO, 1, 0, 0),
468 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
473 .cmd_rcgr = 0x1900c,
487 .cmd_rcgr = 0x1b020,
488 .mnd_width = 0,
501 .cmd_rcgr = 0x1b00c,
515 .cmd_rcgr = 0x1d020,
516 .mnd_width = 0,
529 .cmd_rcgr = 0x1d00c,
543 .cmd_rcgr = 0x1f020,
544 .mnd_width = 0,
557 .cmd_rcgr = 0x1f00c,
571 .cmd_rcgr = 0x21020,
572 .mnd_width = 0,
585 .cmd_rcgr = 0x2100c,
599 .cmd_rcgr = 0x23020,
600 .mnd_width = 0,
613 .cmd_rcgr = 0x2300c,
631 F(19200000, P_XO, 1, 0, 0),
634 F(40000000, P_GPLL0_OUT_MAIN, 15, 0, 0),
636 F(48000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
640 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
641 F(63157895, P_GPLL0_OUT_MAIN, 9.5, 0, 0),
646 .cmd_rcgr = 0x1a00c,
660 .cmd_rcgr = 0x1c00c,
674 .cmd_rcgr = 0x1e00c,
688 .cmd_rcgr = 0x26020,
689 .mnd_width = 0,
702 .cmd_rcgr = 0x2600c,
716 .cmd_rcgr = 0x28020,
717 .mnd_width = 0,
730 .cmd_rcgr = 0x2800c,
744 .cmd_rcgr = 0x2a020,
745 .mnd_width = 0,
758 .cmd_rcgr = 0x2a00c,
772 .cmd_rcgr = 0x2c020,
773 .mnd_width = 0,
786 .cmd_rcgr = 0x2c00c,
800 .cmd_rcgr = 0x2e020,
801 .mnd_width = 0,
814 .cmd_rcgr = 0x2e00c,
828 .cmd_rcgr = 0x30020,
829 .mnd_width = 0,
842 .cmd_rcgr = 0x3000c,
856 .cmd_rcgr = 0x2700c,
870 .cmd_rcgr = 0x2900c,
884 .cmd_rcgr = 0x2b00c,
898 F(19200000, P_XO, 1, 0, 0),
899 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
900 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
905 .cmd_rcgr = 0x64004,
919 .cmd_rcgr = 0x65004,
933 .cmd_rcgr = 0x66004,
947 F(19200000, P_XO, 1, 0, 0),
948 F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0),
949 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
954 .cmd_rcgr = 0x48014,
955 .mnd_width = 0,
968 F(19200000, P_XO, 1, 0, 0),
973 .cmd_rcgr = 0x48044,
974 .mnd_width = 0,
992 .cmd_rcgr = 0x6c000,
1006 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
1011 .cmd_rcgr = 0x33010,
1012 .mnd_width = 0,
1029 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
1030 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
1031 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1036 .cmd_rcgr = 0x14010,
1054 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
1055 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
1060 .cmd_rcgr = 0x16010,
1079 .cmd_rcgr = 0x36010,
1093 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
1094 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1095 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1100 .cmd_rcgr = 0x75018,
1114 F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0),
1115 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1116 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1121 .cmd_rcgr = 0x76028,
1135 F(19200000, P_XO, 1, 0, 0),
1136 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
1137 F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
1138 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1143 .cmd_rcgr = 0xf014,
1157 .cmd_rcgr = 0xf028,
1158 .mnd_width = 0,
1171 F(1200000, P_XO, 16, 0, 0),
1176 .cmd_rcgr = 0x5000c,
1177 .mnd_width = 0,
1190 .halt_reg = 0x8202c,
1193 .enable_reg = 0x8202c,
1194 .enable_mask = BIT(0),
1203 .halt_reg = 0x82028,
1206 .enable_reg = 0x82028,
1207 .enable_mask = BIT(0),
1221 .halt_reg = 0x82024,
1224 .enable_reg = 0x82024,
1225 .enable_mask = BIT(0),
1239 .halt_reg = 0x48090,
1242 .enable_reg = 0x48090,
1243 .enable_mask = BIT(0),
1252 .halt_reg = 0x48094,
1255 .enable_reg = 0x48094,
1256 .enable_mask = BIT(0),
1265 .halt_reg = 0x48004,
1268 .enable_reg = 0x52004,
1278 .halt_reg = 0x4401c,
1281 .enable_reg = 0x4401c,
1282 .enable_mask = BIT(0),
1291 .halt_reg = 0x8a000,
1294 .enable_reg = 0x8a000,
1295 .enable_mask = BIT(0),
1304 .halt_reg = 0x8a03c,
1307 .enable_reg = 0x8a03c,
1308 .enable_mask = BIT(0),
1317 .halt_reg = 0x8a004,
1320 .enable_reg = 0x8a004,
1321 .enable_mask = BIT(0),
1330 .halt_reg = 0x38004,
1332 .hwcg_reg = 0x38004,
1335 .enable_reg = 0x52004,
1347 .enable_reg = 0x5200c,
1357 .halt_reg = 0x17004,
1360 .enable_reg = 0x52004,
1370 .halt_reg = 0x19008,
1373 .enable_reg = 0x19008,
1374 .enable_mask = BIT(0),
1388 .halt_reg = 0x19004,
1391 .enable_reg = 0x19004,
1392 .enable_mask = BIT(0),
1406 .halt_reg = 0x1b008,
1409 .enable_reg = 0x1b008,
1410 .enable_mask = BIT(0),
1424 .halt_reg = 0x1b004,
1427 .enable_reg = 0x1b004,
1428 .enable_mask = BIT(0),
1442 .halt_reg = 0x1d008,
1445 .enable_reg = 0x1d008,
1446 .enable_mask = BIT(0),
1460 .halt_reg = 0x1d004,
1463 .enable_reg = 0x1d004,
1464 .enable_mask = BIT(0),
1478 .halt_reg = 0x1f008,
1481 .enable_reg = 0x1f008,
1482 .enable_mask = BIT(0),
1496 .halt_reg = 0x1f004,
1499 .enable_reg = 0x1f004,
1500 .enable_mask = BIT(0),
1514 .halt_reg = 0x21008,
1517 .enable_reg = 0x21008,
1518 .enable_mask = BIT(0),
1532 .halt_reg = 0x21004,
1535 .enable_reg = 0x21004,
1536 .enable_mask = BIT(0),
1550 .halt_reg = 0x23008,
1553 .enable_reg = 0x23008,
1554 .enable_mask = BIT(0),
1568 .halt_reg = 0x23004,
1571 .enable_reg = 0x23004,
1572 .enable_mask = BIT(0),
1586 .halt_reg = 0x17008,
1589 .enable_reg = 0x52004,
1599 .halt_reg = 0x1a004,
1602 .enable_reg = 0x1a004,
1603 .enable_mask = BIT(0),
1617 .halt_reg = 0x1c004,
1620 .enable_reg = 0x1c004,
1621 .enable_mask = BIT(0),
1635 .halt_reg = 0x1e004,
1638 .enable_reg = 0x1e004,
1639 .enable_mask = BIT(0),
1653 .halt_reg = 0x25004,
1656 .enable_reg = 0x52004,
1666 .halt_reg = 0x26008,
1669 .enable_reg = 0x26008,
1670 .enable_mask = BIT(0),
1684 .halt_reg = 0x26004,
1687 .enable_reg = 0x26004,
1688 .enable_mask = BIT(0),
1702 .halt_reg = 0x28008,
1705 .enable_reg = 0x28008,
1706 .enable_mask = BIT(0),
1720 .halt_reg = 0x28004,
1723 .enable_reg = 0x28004,
1724 .enable_mask = BIT(0),
1738 .halt_reg = 0x2a008,
1741 .enable_reg = 0x2a008,
1742 .enable_mask = BIT(0),
1756 .halt_reg = 0x2a004,
1759 .enable_reg = 0x2a004,
1760 .enable_mask = BIT(0),
1774 .halt_reg = 0x2c008,
1777 .enable_reg = 0x2c008,
1778 .enable_mask = BIT(0),
1792 .halt_reg = 0x2c004,
1795 .enable_reg = 0x2c004,
1796 .enable_mask = BIT(0),
1810 .halt_reg = 0x2e008,
1813 .enable_reg = 0x2e008,
1814 .enable_mask = BIT(0),
1828 .halt_reg = 0x2e004,
1831 .enable_reg = 0x2e004,
1832 .enable_mask = BIT(0),
1846 .halt_reg = 0x30008,
1849 .enable_reg = 0x30008,
1850 .enable_mask = BIT(0),
1864 .halt_reg = 0x30004,
1867 .enable_reg = 0x30004,
1868 .enable_mask = BIT(0),
1882 .halt_reg = 0x25008,
1885 .enable_reg = 0x52004,
1895 .halt_reg = 0x27004,
1898 .enable_reg = 0x27004,
1899 .enable_mask = BIT(0),
1913 .halt_reg = 0x29004,
1916 .enable_reg = 0x29004,
1917 .enable_mask = BIT(0),
1931 .halt_reg = 0x2b004,
1934 .enable_reg = 0x2b004,
1935 .enable_mask = BIT(0),
1949 .halt_reg = 0x5018,
1952 .enable_reg = 0x5018,
1953 .enable_mask = BIT(0),
1967 .halt_reg = 0x64000,
1970 .enable_reg = 0x64000,
1971 .enable_mask = BIT(0),
1985 .halt_reg = 0x65000,
1988 .enable_reg = 0x65000,
1989 .enable_mask = BIT(0),
2003 .halt_reg = 0x66000,
2006 .enable_reg = 0x66000,
2007 .enable_mask = BIT(0),
2021 .halt_reg = 0x46040,
2024 .enable_reg = 0x46040,
2025 .enable_mask = BIT(0),
2034 .halt_reg = 0x71010,
2037 .enable_reg = 0x71010,
2038 .enable_mask = BIT(0),
2047 .halt_reg = 0x7100c,
2050 .enable_reg = 0x7100c,
2051 .enable_mask = BIT(0),
2060 .halt_reg = 0x71004,
2063 .enable_reg = 0x71004,
2064 .enable_mask = BIT(0),
2073 .halt_reg = 0x71018,
2076 .enable_reg = 0x71018,
2077 .enable_mask = BIT(0),
2086 .halt_reg = 0x48000,
2089 .enable_reg = 0x52004,
2104 .halt_reg = 0x48010,
2107 .enable_reg = 0x48010,
2108 .enable_mask = BIT(0),
2117 .halt_reg = 0x48008,
2120 .enable_reg = 0x48008,
2121 .enable_mask = BIT(0),
2135 .halt_reg = 0x4800c,
2138 .enable_reg = 0x4800c,
2139 .enable_mask = BIT(0),
2148 .halt_reg = 0x9004,
2151 .enable_reg = 0x9004,
2152 .enable_mask = BIT(0),
2167 .halt_reg = 0x9030,
2170 .enable_reg = 0x9030,
2171 .enable_mask = BIT(0),
2180 .halt_reg = 0x900c,
2183 .enable_reg = 0x900c,
2184 .enable_mask = BIT(0),
2193 .halt_reg = 0x9000,
2196 .enable_reg = 0x9000,
2197 .enable_mask = BIT(0),
2206 .halt_reg = 0x8a00c,
2209 .enable_reg = 0x8a00c,
2210 .enable_mask = BIT(0),
2219 .halt_reg = 0x6b014,
2222 .enable_reg = 0x6b014,
2223 .enable_mask = BIT(0),
2237 .halt_reg = 0x6b010,
2240 .enable_reg = 0x6b010,
2241 .enable_mask = BIT(0),
2250 .halt_reg = 0x6b00c,
2253 .enable_reg = 0x6b00c,
2254 .enable_mask = BIT(0),
2263 .halt_reg = 0x6b018,
2266 .enable_reg = 0x6b018,
2267 .enable_mask = BIT(0),
2276 .halt_reg = 0x6b008,
2279 .enable_reg = 0x6b008,
2280 .enable_mask = BIT(0),
2289 .halt_reg = 0x6f004,
2292 .enable_reg = 0x6f004,
2293 .enable_mask = BIT(0),
2307 .halt_reg = 0x3300c,
2310 .enable_reg = 0x3300c,
2311 .enable_mask = BIT(0),
2325 .halt_reg = 0x33004,
2328 .enable_reg = 0x33004,
2329 .enable_mask = BIT(0),
2338 .halt_reg = 0x33008,
2341 .enable_reg = 0x33008,
2342 .enable_mask = BIT(0),
2351 .halt_reg = 0x34004,
2354 .enable_reg = 0x52004,
2364 .halt_reg = 0x14008,
2367 .enable_reg = 0x14008,
2368 .enable_mask = BIT(0),
2377 .halt_reg = 0x14004,
2380 .enable_reg = 0x14004,
2381 .enable_mask = BIT(0),
2395 .halt_reg = 0x16008,
2398 .enable_reg = 0x16008,
2399 .enable_mask = BIT(0),
2408 .halt_reg = 0x16004,
2411 .enable_reg = 0x16004,
2412 .enable_mask = BIT(0),
2426 .halt_reg = 0x36004,
2429 .enable_reg = 0x36004,
2430 .enable_mask = BIT(0),
2439 .halt_reg = 0x3600c,
2442 .enable_reg = 0x3600c,
2443 .enable_mask = BIT(0),
2452 .halt_reg = 0x36008,
2455 .enable_reg = 0x36008,
2456 .enable_mask = BIT(0),
2470 .halt_reg = 0x7500c,
2473 .enable_reg = 0x7500c,
2474 .enable_mask = BIT(0),
2483 .halt_reg = 0x75008,
2486 .enable_reg = 0x75008,
2487 .enable_mask = BIT(0),
2501 .halt_reg = 0x7600c,
2504 .enable_reg = 0x7600c,
2505 .enable_mask = BIT(0),
2514 .halt_reg = 0x76040,
2517 .enable_reg = 0x76040,
2518 .enable_mask = BIT(0),
2527 .halt_reg = 0x75014,
2530 .enable_reg = 0x75014,
2531 .enable_mask = BIT(0),
2540 .halt_reg = 0x7605c,
2543 .enable_reg = 0x7605c,
2544 .enable_mask = BIT(0),
2553 .halt_reg = 0x75010,
2556 .enable_reg = 0x75010,
2557 .enable_mask = BIT(0),
2566 .halt_reg = 0x76008,
2569 .enable_reg = 0x76008,
2570 .enable_mask = BIT(0),
2584 .halt_reg = 0xf008,
2587 .enable_reg = 0xf008,
2588 .enable_mask = BIT(0),
2602 .halt_reg = 0xf010,
2605 .enable_reg = 0xf010,
2606 .enable_mask = BIT(0),
2620 .halt_reg = 0xf00c,
2623 .enable_reg = 0xf00c,
2624 .enable_mask = BIT(0),
2633 .halt_reg = 0x50000,
2636 .enable_reg = 0x50000,
2637 .enable_mask = BIT(0),
2651 .halt_reg = 0x50004,
2654 .enable_reg = 0x50004,
2655 .enable_mask = BIT(0),
2664 .halt_reg = 0x6a004,
2667 .enable_reg = 0x6a004,
2668 .enable_mask = BIT(0),
2677 .halt_reg = 0x88000,
2679 .enable_reg = 0x88000,
2680 .enable_mask = BIT(0),
2691 .halt_reg = 0x88004,
2693 .enable_reg = 0x88004,
2694 .enable_mask = BIT(0),
2705 .halt_reg = 0x88008,
2707 .enable_reg = 0x88008,
2708 .enable_mask = BIT(0),
2719 .halt_reg = 0x8800c,
2721 .enable_reg = 0x8800c,
2722 .enable_mask = BIT(0),
2733 .halt_reg = 0x88014,
2735 .enable_reg = 0x88014,
2736 .enable_mask = BIT(0),
2747 .gdscr = 0x6b004,
2748 .gds_hw_ctrl = 0x0,
2757 .gdscr = 0x75004,
2758 .gds_hw_ctrl = 0x0,
2767 .gdscr = 0xf004,
2768 .gds_hw_ctrl = 0x0,
2956 [GCC_BLSP1_QUP1_BCR] = { 0x19000 },
2957 [GCC_BLSP1_QUP2_BCR] = { 0x1b000 },
2958 [GCC_BLSP1_QUP3_BCR] = { 0x1d000 },
2959 [GCC_BLSP1_QUP4_BCR] = { 0x1f000 },
2960 [GCC_BLSP1_QUP5_BCR] = { 0x21000 },
2961 [GCC_BLSP1_QUP6_BCR] = { 0x23000 },
2962 [GCC_BLSP2_QUP1_BCR] = { 0x26000 },
2963 [GCC_BLSP2_QUP2_BCR] = { 0x28000 },
2964 [GCC_BLSP2_QUP3_BCR] = { 0x2a000 },
2965 [GCC_BLSP2_QUP4_BCR] = { 0x2c000 },
2966 [GCC_BLSP2_QUP5_BCR] = { 0x2e000 },
2967 [GCC_BLSP2_QUP6_BCR] = { 0x30000 },
2968 [GCC_PCIE_0_BCR] = { 0x6b000 },
2969 [GCC_PDM_BCR] = { 0x33000 },
2970 [GCC_SDCC2_BCR] = { 0x14000 },
2971 [GCC_SDCC4_BCR] = { 0x16000 },
2972 [GCC_TSIF_BCR] = { 0x36000 },
2973 [GCC_UFS_BCR] = { 0x75000 },
2974 [GCC_USB_30_BCR] = { 0xf000 },
2975 [GCC_SYSTEM_NOC_BCR] = { 0x4000 },
2976 [GCC_CONFIG_NOC_BCR] = { 0x5000 },
2977 [GCC_AHB2PHY_EAST_BCR] = { 0x7000 },
2978 [GCC_IMEM_BCR] = { 0x8000 },
2979 [GCC_PIMEM_BCR] = { 0xa000 },
2980 [GCC_MMSS_BCR] = { 0xb000 },
2981 [GCC_QDSS_BCR] = { 0xc000 },
2982 [GCC_WCSS_BCR] = { 0x11000 },
2983 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
2984 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
2985 [GCC_BLSP1_BCR] = { 0x17000 },
2986 [GCC_BLSP1_UART1_BCR] = { 0x1a000 },
2987 [GCC_BLSP1_UART2_BCR] = { 0x1c000 },
2988 [GCC_BLSP1_UART3_BCR] = { 0x1e000 },
2989 [GCC_CM_PHY_REFGEN1_BCR] = { 0x22000 },
2990 [GCC_CM_PHY_REFGEN2_BCR] = { 0x24000 },
2991 [GCC_BLSP2_BCR] = { 0x25000 },
2992 [GCC_BLSP2_UART1_BCR] = { 0x27000 },
2993 [GCC_BLSP2_UART2_BCR] = { 0x29000 },
2994 [GCC_BLSP2_UART3_BCR] = { 0x2b000 },
2995 [GCC_SRAM_SENSOR_BCR] = { 0x2d000 },
2996 [GCC_PRNG_BCR] = { 0x34000 },
2997 [GCC_TSIF_0_RESET] = { 0x36024 },
2998 [GCC_TSIF_1_RESET] = { 0x36028 },
2999 [GCC_TCSR_BCR] = { 0x37000 },
3000 [GCC_BOOT_ROM_BCR] = { 0x38000 },
3001 [GCC_MSG_RAM_BCR] = { 0x39000 },
3002 [GCC_TLMM_BCR] = { 0x3a000 },
3003 [GCC_MPM_BCR] = { 0x3b000 },
3004 [GCC_SEC_CTRL_BCR] = { 0x3d000 },
3005 [GCC_SPMI_BCR] = { 0x3f000 },
3006 [GCC_SPDM_BCR] = { 0x40000 },
3007 [GCC_CE1_BCR] = { 0x41000 },
3008 [GCC_BIMC_BCR] = { 0x44000 },
3009 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x49000 },
3010 [GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x49008 },
3011 [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x49010 },
3012 [GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x49018 },
3013 [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x4a000 },
3014 [GCC_CNOC_PERIPH_BUS_TIMEOUT1_BCR] = { 0x4a004 },
3015 [GCC_CNOC_PERIPH_BUS_TIMEOUT2_BCR] = { 0x4a00c },
3016 [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x4b000 },
3017 [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x4b008 },
3018 [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x4b010 },
3019 [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x4b018 },
3020 [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x4b020 },
3021 [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x4b028 },
3022 [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x4b030 },
3023 [GCC_CNOC_BUS_TIMEOUT7_BCR] = { 0x4b038 },
3024 [GCC_APB2JTAG_BCR] = { 0x4c000 },
3025 [GCC_RBCPR_CX_BCR] = { 0x4e000 },
3026 [GCC_RBCPR_MX_BCR] = { 0x4f000 },
3027 [GCC_USB3_PHY_BCR] = { 0x50020 },
3028 [GCC_USB3PHY_PHY_BCR] = { 0x50024 },
3029 [GCC_USB3_DP_PHY_BCR] = { 0x50028 },
3030 [GCC_SSC_BCR] = { 0x63000 },
3031 [GCC_SSC_RESET] = { 0x63020 },
3032 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3033 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
3034 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3035 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
3036 [GCC_PCIE_PHY_BCR] = { 0x6f000 },
3037 [GCC_PCIE_PHY_NOCSR_COM_PHY_BCR] = { 0x6f00c },
3038 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f010 },
3039 [GCC_PCIE_PHY_COM_BCR] = { 0x6f014 },
3040 [GCC_GPU_BCR] = { 0x71000 },
3041 [GCC_SPSS_BCR] = { 0x72000 },
3042 [GCC_OBT_ODT_BCR] = { 0x73000 },
3043 [GCC_MSS_RESTART] = { 0x79000 },
3044 [GCC_VS_BCR] = { 0x7a000 },
3045 [GCC_MSS_VS_RESET] = { 0x7a100 },
3046 [GCC_GPU_VS_RESET] = { 0x7a104 },
3047 [GCC_APC0_VS_RESET] = { 0x7a108 },
3048 [GCC_APC1_VS_RESET] = { 0x7a10c },
3049 [GCC_CNOC_BUS_TIMEOUT8_BCR] = { 0x80000 },
3050 [GCC_CNOC_BUS_TIMEOUT9_BCR] = { 0x80008 },
3051 [GCC_CNOC_BUS_TIMEOUT10_BCR] = { 0x80010 },
3052 [GCC_CNOC_BUS_TIMEOUT11_BCR] = { 0x80018 },
3053 [GCC_CNOC_BUS_TIMEOUT12_BCR] = { 0x80020 },
3054 [GCC_CNOC_BUS_TIMEOUT13_BCR] = { 0x80028 },
3055 [GCC_CNOC_BUS_TIMEOUT14_BCR] = { 0x80030 },
3056 [GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x80038 },
3057 [GCC_AGGRE1_NOC_BCR] = { 0x82000 },
3058 [GCC_AGGRE2_NOC_BCR] = { 0x83000 },
3059 [GCC_DCC_BCR] = { 0x84000 },
3060 [GCC_QREFS_VBG_CAL_BCR] = { 0x88028 },
3061 [GCC_IPA_BCR] = { 0x89000 },
3062 [GCC_GLM_BCR] = { 0x8b000 },
3063 [GCC_SKL_BCR] = { 0x8c000 },
3064 [GCC_MSMPU_BCR] = { 0x8d000 },
3071 .max_register = 0x8f000,
3104 ret = regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21)); in gcc_msm8998_probe()