Lines Matching +full:0 +full:x2c000
50 { P_XO, 0 },
60 { P_XO, 0 },
70 { P_XO, 0 },
82 { P_XO, 0 },
94 { P_XO, 0 },
106 { P_XO, 0 },
120 { P_XO, 0 },
134 { P_XO, 0 },
152 { P_XO, 0 },
183 .offset = 0x00000,
186 .enable_reg = 0x52000,
187 .enable_mask = BIT(0),
209 .offset = 0x00000,
222 .enable_reg = 0x5200c,
223 .enable_mask = BIT(0),
237 .enable_reg = 0x5200c,
250 .offset = 0x77000,
253 .enable_reg = 0x52000,
265 .offset = 0x77000,
276 F(19200000, P_XO, 1, 0, 0),
277 F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
278 F(100000000, P_GPLL0, 6, 0, 0),
279 F(150000000, P_GPLL0, 4, 0, 0),
280 F(200000000, P_GPLL0, 3, 0, 0),
281 F(240000000, P_GPLL0, 2.5, 0, 0),
286 .cmd_rcgr = 0x0401c,
299 F(19200000, P_XO, 1, 0, 0),
300 F(37500000, P_GPLL0, 16, 0, 0),
301 F(75000000, P_GPLL0, 8, 0, 0),
306 .cmd_rcgr = 0x0500c,
319 F(19200000, P_XO, 1, 0, 0),
320 F(37500000, P_GPLL0, 16, 0, 0),
321 F(50000000, P_GPLL0, 12, 0, 0),
322 F(75000000, P_GPLL0, 8, 0, 0),
323 F(100000000, P_GPLL0, 6, 0, 0),
328 .cmd_rcgr = 0x06014,
341 F(19200000, P_XO, 1, 0, 0),
342 F(120000000, P_GPLL0, 5, 0, 0),
343 F(150000000, P_GPLL0, 4, 0, 0),
348 .cmd_rcgr = 0x0f014,
362 F(19200000, P_XO, 1, 0, 0),
367 .cmd_rcgr = 0x0f028,
380 F(1200000, P_XO, 16, 0, 0),
385 .cmd_rcgr = 0x5000c,
398 F(120000000, P_GPLL0, 5, 0, 0),
403 .cmd_rcgr = 0x12010,
417 .cmd_rcgr = 0x12024,
434 F(50000000, P_GPLL0, 12, 0, 0),
435 F(96000000, P_GPLL4, 4, 0, 0),
436 F(192000000, P_GPLL4, 2, 0, 0),
437 F(384000000, P_GPLL4, 1, 0, 0),
442 .cmd_rcgr = 0x13010,
456 F(19200000, P_XO, 1, 0, 0),
457 F(150000000, P_GPLL0, 4, 0, 0),
458 F(300000000, P_GPLL0, 2, 0, 0),
463 .cmd_rcgr = 0x13024,
480 F(50000000, P_GPLL0, 12, 0, 0),
481 F(100000000, P_GPLL0, 6, 0, 0),
482 F(200000000, P_GPLL0, 3, 0, 0),
487 .cmd_rcgr = 0x14010,
501 .cmd_rcgr = 0x15010,
519 F(50000000, P_GPLL0, 12, 0, 0),
520 F(100000000, P_GPLL0, 6, 0, 0),
525 .cmd_rcgr = 0x16010,
540 F(4800000, P_XO, 4, 0, 0),
541 F(9600000, P_XO, 2, 0, 0),
543 F(19200000, P_XO, 1, 0, 0),
545 F(50000000, P_GPLL0, 12, 0, 0),
550 .cmd_rcgr = 0x1900c,
564 F(19200000, P_XO, 1, 0, 0),
565 F(50000000, P_GPLL0, 12, 0, 0),
570 .cmd_rcgr = 0x19020,
587 F(19200000, P_XO, 1, 0, 0),
590 F(40000000, P_GPLL0, 15, 0, 0),
592 F(48000000, P_GPLL0, 12.5, 0, 0),
596 F(60000000, P_GPLL0, 10, 0, 0),
597 F(63157895, P_GPLL0, 9.5, 0, 0),
602 .cmd_rcgr = 0x1a00c,
616 .cmd_rcgr = 0x1b00c,
630 .cmd_rcgr = 0x1b020,
643 .cmd_rcgr = 0x1c00c,
657 .cmd_rcgr = 0x1d00c,
671 .cmd_rcgr = 0x1d020,
684 .cmd_rcgr = 0x1e00c,
698 .cmd_rcgr = 0x1f00c,
712 .cmd_rcgr = 0x1f020,
725 .cmd_rcgr = 0x2000c,
739 .cmd_rcgr = 0x2100c,
753 .cmd_rcgr = 0x21020,
766 .cmd_rcgr = 0x2200c,
780 .cmd_rcgr = 0x2300c,
794 .cmd_rcgr = 0x23020,
807 .cmd_rcgr = 0x2400c,
821 .cmd_rcgr = 0x2600c,
835 .cmd_rcgr = 0x26020,
848 .cmd_rcgr = 0x2700c,
862 .cmd_rcgr = 0x2800c,
876 .cmd_rcgr = 0x28020,
889 .cmd_rcgr = 0x2900c,
903 .cmd_rcgr = 0x2a00c,
917 .cmd_rcgr = 0x2a020,
930 .cmd_rcgr = 0x2b00c,
944 .cmd_rcgr = 0x2c00c,
958 .cmd_rcgr = 0x2c020,
971 .cmd_rcgr = 0x2d00c,
985 .cmd_rcgr = 0x2e00c,
999 .cmd_rcgr = 0x2e020,
1012 .cmd_rcgr = 0x2f00c,
1026 .cmd_rcgr = 0x3000c,
1040 .cmd_rcgr = 0x30020,
1053 .cmd_rcgr = 0x3100c,
1067 F(60000000, P_GPLL0, 10, 0, 0),
1072 .cmd_rcgr = 0x33010,
1090 .cmd_rcgr = 0x36010,
1104 .cmd_rcgr = 0x43014,
1116 .cmd_rcgr = 0x48040,
1129 .cmd_rcgr = 0x48058,
1141 F(19200000, P_XO, 1, 0, 0),
1142 F(100000000, P_GPLL0, 6, 0, 0),
1143 F(200000000, P_GPLL0, 3, 0, 0),
1148 .cmd_rcgr = 0x64004,
1162 .cmd_rcgr = 0x65004,
1176 .cmd_rcgr = 0x66004,
1195 .cmd_rcgr = 0x6c000,
1209 F(100000000, P_GPLL0, 6, 0, 0),
1210 F(200000000, P_GPLL0, 3, 0, 0),
1211 F(240000000, P_GPLL0, 2.5, 0, 0),
1216 .cmd_rcgr = 0x75024,
1230 F(19200000, P_XO, 1, 0, 0),
1231 F(150000000, P_GPLL0, 4, 0, 0),
1232 F(300000000, P_GPLL0, 2, 0, 0),
1237 .cmd_rcgr = 0x76014,
1250 F(75000000, P_GPLL0, 8, 0, 0),
1251 F(150000000, P_GPLL0, 4, 0, 0),
1252 F(256000000, P_GPLL4, 1.5, 0, 0),
1253 F(300000000, P_GPLL0, 2, 0, 0),
1258 .cmd_rcgr = 0x8b00c,
1271 .halt_reg = 0x0f03c,
1273 .enable_reg = 0x0f03c,
1274 .enable_mask = BIT(0),
1286 .halt_reg = 0x75038,
1288 .enable_reg = 0x75038,
1289 .enable_mask = BIT(0),
1301 .halt_reg = 0x6010,
1303 .enable_reg = 0x6010,
1304 .enable_mask = BIT(0),
1316 .halt_reg = 0x9008,
1318 .enable_reg = 0x9008,
1319 .enable_mask = BIT(0),
1331 .halt_reg = 0x9010,
1333 .enable_reg = 0x9010,
1334 .enable_mask = BIT(0),
1344 .halt_reg = 0x0f008,
1346 .enable_reg = 0x0f008,
1347 .enable_mask = BIT(0),
1359 .halt_reg = 0x0f00c,
1361 .enable_reg = 0x0f00c,
1362 .enable_mask = BIT(0),
1374 .halt_reg = 0x0f010,
1376 .enable_reg = 0x0f010,
1377 .enable_mask = BIT(0),
1389 .halt_reg = 0x50000,
1391 .enable_reg = 0x50000,
1392 .enable_mask = BIT(0),
1404 .halt_reg = 0x50004,
1407 .enable_reg = 0x50004,
1408 .enable_mask = BIT(0),
1420 .halt_reg = 0x12004,
1422 .enable_reg = 0x12004,
1423 .enable_mask = BIT(0),
1435 .halt_reg = 0x12008,
1437 .enable_reg = 0x12008,
1438 .enable_mask = BIT(0),
1450 .halt_reg = 0x1200c,
1452 .enable_reg = 0x1200c,
1453 .enable_mask = BIT(0),
1465 .halt_reg = 0x6a004,
1467 .enable_reg = 0x6a004,
1468 .enable_mask = BIT(0),
1480 .halt_reg = 0x13004,
1482 .enable_reg = 0x13004,
1483 .enable_mask = BIT(0),
1495 .halt_reg = 0x13008,
1497 .enable_reg = 0x13008,
1498 .enable_mask = BIT(0),
1510 .halt_reg = 0x13038,
1512 .enable_reg = 0x13038,
1513 .enable_mask = BIT(0),
1525 .halt_reg = 0x14004,
1527 .enable_reg = 0x14004,
1528 .enable_mask = BIT(0),
1540 .halt_reg = 0x14008,
1542 .enable_reg = 0x14008,
1543 .enable_mask = BIT(0),
1555 .halt_reg = 0x15004,
1557 .enable_reg = 0x15004,
1558 .enable_mask = BIT(0),
1570 .halt_reg = 0x15008,
1572 .enable_reg = 0x15008,
1573 .enable_mask = BIT(0),
1585 .halt_reg = 0x16004,
1587 .enable_reg = 0x16004,
1588 .enable_mask = BIT(0),
1600 .halt_reg = 0x16008,
1602 .enable_reg = 0x16008,
1603 .enable_mask = BIT(0),
1615 .halt_reg = 0x17004,
1618 .enable_reg = 0x52004,
1631 .halt_reg = 0x17008,
1634 .enable_reg = 0x52004,
1647 .halt_reg = 0x19004,
1649 .enable_reg = 0x19004,
1650 .enable_mask = BIT(0),
1662 .halt_reg = 0x19008,
1664 .enable_reg = 0x19008,
1665 .enable_mask = BIT(0),
1677 .halt_reg = 0x1a004,
1679 .enable_reg = 0x1a004,
1680 .enable_mask = BIT(0),
1692 .halt_reg = 0x1b004,
1694 .enable_reg = 0x1b004,
1695 .enable_mask = BIT(0),
1707 .halt_reg = 0x1b008,
1709 .enable_reg = 0x1b008,
1710 .enable_mask = BIT(0),
1722 .halt_reg = 0x1c004,
1724 .enable_reg = 0x1c004,
1725 .enable_mask = BIT(0),
1737 .halt_reg = 0x1d004,
1739 .enable_reg = 0x1d004,
1740 .enable_mask = BIT(0),
1752 .halt_reg = 0x1d008,
1754 .enable_reg = 0x1d008,
1755 .enable_mask = BIT(0),
1767 .halt_reg = 0x1e004,
1769 .enable_reg = 0x1e004,
1770 .enable_mask = BIT(0),
1782 .halt_reg = 0x1f004,
1784 .enable_reg = 0x1f004,
1785 .enable_mask = BIT(0),
1797 .halt_reg = 0x1f008,
1799 .enable_reg = 0x1f008,
1800 .enable_mask = BIT(0),
1812 .halt_reg = 0x20004,
1814 .enable_reg = 0x20004,
1815 .enable_mask = BIT(0),
1827 .halt_reg = 0x21004,
1829 .enable_reg = 0x21004,
1830 .enable_mask = BIT(0),
1842 .halt_reg = 0x21008,
1844 .enable_reg = 0x21008,
1845 .enable_mask = BIT(0),
1857 .halt_reg = 0x22004,
1859 .enable_reg = 0x22004,
1860 .enable_mask = BIT(0),
1872 .halt_reg = 0x23004,
1874 .enable_reg = 0x23004,
1875 .enable_mask = BIT(0),
1887 .halt_reg = 0x23008,
1889 .enable_reg = 0x23008,
1890 .enable_mask = BIT(0),
1902 .halt_reg = 0x24004,
1904 .enable_reg = 0x24004,
1905 .enable_mask = BIT(0),
1917 .halt_reg = 0x25004,
1920 .enable_reg = 0x52004,
1933 .halt_reg = 0x25008,
1936 .enable_reg = 0x52004,
1949 .halt_reg = 0x26004,
1951 .enable_reg = 0x26004,
1952 .enable_mask = BIT(0),
1964 .halt_reg = 0x26008,
1966 .enable_reg = 0x26008,
1967 .enable_mask = BIT(0),
1979 .halt_reg = 0x27004,
1981 .enable_reg = 0x27004,
1982 .enable_mask = BIT(0),
1994 .halt_reg = 0x28004,
1996 .enable_reg = 0x28004,
1997 .enable_mask = BIT(0),
2009 .halt_reg = 0x28008,
2011 .enable_reg = 0x28008,
2012 .enable_mask = BIT(0),
2024 .halt_reg = 0x29004,
2026 .enable_reg = 0x29004,
2027 .enable_mask = BIT(0),
2039 .halt_reg = 0x2a004,
2041 .enable_reg = 0x2a004,
2042 .enable_mask = BIT(0),
2054 .halt_reg = 0x2a008,
2056 .enable_reg = 0x2a008,
2057 .enable_mask = BIT(0),
2069 .halt_reg = 0x2b004,
2071 .enable_reg = 0x2b004,
2072 .enable_mask = BIT(0),
2084 .halt_reg = 0x2c004,
2086 .enable_reg = 0x2c004,
2087 .enable_mask = BIT(0),
2099 .halt_reg = 0x2c008,
2101 .enable_reg = 0x2c008,
2102 .enable_mask = BIT(0),
2114 .halt_reg = 0x2d004,
2116 .enable_reg = 0x2d004,
2117 .enable_mask = BIT(0),
2129 .halt_reg = 0x2e004,
2131 .enable_reg = 0x2e004,
2132 .enable_mask = BIT(0),
2144 .halt_reg = 0x2e008,
2146 .enable_reg = 0x2e008,
2147 .enable_mask = BIT(0),
2159 .halt_reg = 0x2f004,
2161 .enable_reg = 0x2f004,
2162 .enable_mask = BIT(0),
2174 .halt_reg = 0x30004,
2176 .enable_reg = 0x30004,
2177 .enable_mask = BIT(0),
2189 .halt_reg = 0x30008,
2191 .enable_reg = 0x30008,
2192 .enable_mask = BIT(0),
2204 .halt_reg = 0x31004,
2206 .enable_reg = 0x31004,
2207 .enable_mask = BIT(0),
2219 .halt_reg = 0x33004,
2221 .enable_reg = 0x33004,
2222 .enable_mask = BIT(0),
2234 .halt_reg = 0x3300c,
2236 .enable_reg = 0x3300c,
2237 .enable_mask = BIT(0),
2249 .halt_reg = 0x34004,
2252 .enable_reg = 0x52004,
2265 .halt_reg = 0x36004,
2267 .enable_reg = 0x36004,
2268 .enable_mask = BIT(0),
2280 .halt_reg = 0x36008,
2282 .enable_reg = 0x36008,
2283 .enable_mask = BIT(0),
2295 .halt_reg = 0x3600c,
2297 .enable_reg = 0x3600c,
2298 .enable_mask = BIT(0),
2310 .halt_reg = 0x38004,
2313 .enable_reg = 0x52004,
2326 .halt_reg = 0x46018,
2328 .enable_reg = 0x46018,
2329 .enable_mask = BIT(0),
2339 .halt_reg = 0x4800c,
2341 .enable_reg = 0x4800c,
2342 .enable_mask = BIT(0),
2354 .halt_reg = 0x64000,
2356 .enable_reg = 0x64000,
2357 .enable_mask = BIT(0),
2369 .halt_reg = 0x65000,
2371 .enable_reg = 0x65000,
2372 .enable_mask = BIT(0),
2384 .halt_reg = 0x66000,
2386 .enable_reg = 0x66000,
2387 .enable_mask = BIT(0),
2399 .halt_reg = 0x6b008,
2401 .enable_reg = 0x6b008,
2402 .enable_mask = BIT(0),
2414 .halt_reg = 0x6b00c,
2416 .enable_reg = 0x6b00c,
2417 .enable_mask = BIT(0),
2429 .halt_reg = 0x6b010,
2431 .enable_reg = 0x6b010,
2432 .enable_mask = BIT(0),
2444 .halt_reg = 0x6b014,
2446 .enable_reg = 0x6b014,
2447 .enable_mask = BIT(0),
2459 .halt_reg = 0x6b018,
2462 .enable_reg = 0x6b018,
2463 .enable_mask = BIT(0),
2475 .halt_reg = 0x6d008,
2477 .enable_reg = 0x6d008,
2478 .enable_mask = BIT(0),
2490 .halt_reg = 0x6d00c,
2492 .enable_reg = 0x6d00c,
2493 .enable_mask = BIT(0),
2505 .halt_reg = 0x6d010,
2507 .enable_reg = 0x6d010,
2508 .enable_mask = BIT(0),
2520 .halt_reg = 0x6d014,
2522 .enable_reg = 0x6d014,
2523 .enable_mask = BIT(0),
2535 .halt_reg = 0x6d018,
2538 .enable_reg = 0x6d018,
2539 .enable_mask = BIT(0),
2551 .halt_reg = 0x6e008,
2553 .enable_reg = 0x6e008,
2554 .enable_mask = BIT(0),
2566 .halt_reg = 0x6e00c,
2568 .enable_reg = 0x6e00c,
2569 .enable_mask = BIT(0),
2581 .halt_reg = 0x6e010,
2583 .enable_reg = 0x6e010,
2584 .enable_mask = BIT(0),
2596 .halt_reg = 0x6e014,
2598 .enable_reg = 0x6e014,
2599 .enable_mask = BIT(0),
2611 .halt_reg = 0x6e018,
2614 .enable_reg = 0x6e018,
2615 .enable_mask = BIT(0),
2627 .halt_reg = 0x6f004,
2629 .enable_reg = 0x6f004,
2630 .enable_mask = BIT(0),
2642 .halt_reg = 0x6f008,
2644 .enable_reg = 0x6f008,
2645 .enable_mask = BIT(0),
2657 .halt_reg = 0x75008,
2659 .enable_reg = 0x75008,
2660 .enable_mask = BIT(0),
2672 .halt_reg = 0x7500c,
2674 .enable_reg = 0x7500c,
2675 .enable_mask = BIT(0),
2699 .halt_reg = 0x75010,
2701 .enable_reg = 0x75010,
2702 .enable_mask = BIT(0),
2726 .halt_reg = 0x7d010,
2729 .enable_reg = 0x7d010,
2730 .enable_mask = BIT(0),
2739 .halt_reg = 0x7d014,
2742 .enable_reg = 0x7d014,
2743 .enable_mask = BIT(0),
2752 .halt_reg = 0x75014,
2754 .enable_reg = 0x75014,
2755 .enable_mask = BIT(0),
2767 .halt_reg = 0x75018,
2770 .enable_reg = 0x75018,
2771 .enable_mask = BIT(0),
2783 .halt_reg = 0x7501c,
2786 .enable_reg = 0x7501c,
2787 .enable_mask = BIT(0),
2799 .halt_reg = 0x75020,
2802 .enable_reg = 0x75020,
2803 .enable_mask = BIT(0),
2827 .halt_reg = 0x7600c,
2829 .enable_reg = 0x7600c,
2830 .enable_mask = BIT(0),
2842 .halt_reg = 0x76010,
2844 .enable_reg = 0x76010,
2845 .enable_mask = BIT(0),
2859 .enable_reg = 0x76030,
2860 .enable_mask = BIT(0),
2871 .enable_reg = 0x76034,
2872 .enable_mask = BIT(0),
2881 .halt_reg = 0x81008,
2883 .enable_reg = 0x81008,
2884 .enable_mask = BIT(0),
2896 .halt_reg = 0x8100c,
2898 .enable_reg = 0x8100c,
2899 .enable_mask = BIT(0),
2911 .halt_reg = 0x81014,
2913 .enable_reg = 0x81014,
2914 .enable_mask = BIT(0),
2926 .halt_reg = 0x81018,
2928 .enable_reg = 0x81018,
2929 .enable_mask = BIT(0),
2941 .halt_reg = 0x82014,
2943 .enable_reg = 0x82014,
2944 .enable_mask = BIT(0),
2955 .halt_reg = 0x83014,
2957 .enable_reg = 0x83014,
2958 .enable_mask = BIT(0),
2970 .halt_reg = 0x83018,
2972 .enable_reg = 0x83018,
2973 .enable_mask = BIT(0),
2985 .halt_reg = 0x84004,
2987 .enable_reg = 0x84004,
2988 .enable_mask = BIT(0),
2999 .halt_reg = 0x85000,
3001 .enable_reg = 0x85000,
3002 .enable_mask = BIT(0),
3013 .halt_reg = 0x8b004,
3015 .enable_reg = 0x8b004,
3016 .enable_mask = BIT(0),
3028 .halt_reg = 0x8b008,
3030 .enable_reg = 0x8b008,
3031 .enable_mask = BIT(0),
3043 .halt_reg = 0x8800C,
3045 .enable_reg = 0x8800C,
3046 .enable_mask = BIT(0),
3060 .halt_reg = 0x88000,
3062 .enable_reg = 0x88000,
3063 .enable_mask = BIT(0),
3077 .halt_reg = 0x88004,
3079 .enable_reg = 0x88004,
3080 .enable_mask = BIT(0),
3094 .halt_reg = 0x88008,
3096 .enable_reg = 0x88008,
3097 .enable_mask = BIT(0),
3111 .halt_reg = 0x88010,
3113 .enable_reg = 0x88010,
3114 .enable_mask = BIT(0),
3128 .halt_reg = 0x88014,
3130 .enable_reg = 0x88014,
3131 .enable_mask = BIT(0),
3145 .halt_reg = 0x88018,
3147 .enable_reg = 0x88018,
3148 .enable_mask = BIT(0),
3162 .halt_reg = 0x8a000,
3164 .enable_reg = 0x8a000,
3165 .enable_mask = BIT(0),
3176 .halt_reg = 0x8a004,
3178 .enable_reg = 0x8a004,
3179 .enable_mask = BIT(0),
3190 .halt_reg = 0x8a024,
3192 .enable_reg = 0x8a024,
3193 .enable_mask = BIT(0),
3204 .halt_reg = 0x8a028,
3206 .enable_reg = 0x8a028,
3207 .enable_mask = BIT(0),
3226 .gdscr = 0x81004,
3227 .gds_hw_ctrl = 0x81028,
3236 .gdscr = 0x7d024,
3245 .gdscr = 0x7d034,
3254 .gdscr = 0x7d038,
3263 .gdscr = 0xf004,
3271 .gdscr = 0x6b004,
3279 .gdscr = 0x6d004,
3287 .gdscr = 0x6e004,
3295 .gdscr = 0x75004,
3512 [GCC_SYSTEM_NOC_BCR] = { 0x4000 },
3513 [GCC_CONFIG_NOC_BCR] = { 0x5000 },
3514 [GCC_PERIPH_NOC_BCR] = { 0x6000 },
3515 [GCC_IMEM_BCR] = { 0x8000 },
3516 [GCC_MMSS_BCR] = { 0x9000 },
3517 [GCC_PIMEM_BCR] = { 0x0a000 },
3518 [GCC_QDSS_BCR] = { 0x0c000 },
3519 [GCC_USB_30_BCR] = { 0x0f000 },
3520 [GCC_USB_20_BCR] = { 0x12000 },
3521 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12038 },
3522 [GCC_QUSB2PHY_SEC_BCR] = { 0x1203c },
3523 [GCC_USB3_PHY_BCR] = { 0x50020 },
3524 [GCC_USB3PHY_PHY_BCR] = { 0x50024 },
3525 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3526 [GCC_SDCC1_BCR] = { 0x13000 },
3527 [GCC_SDCC2_BCR] = { 0x14000 },
3528 [GCC_SDCC3_BCR] = { 0x15000 },
3529 [GCC_SDCC4_BCR] = { 0x16000 },
3530 [GCC_BLSP1_BCR] = { 0x17000 },
3531 [GCC_BLSP1_QUP1_BCR] = { 0x19000 },
3532 [GCC_BLSP1_UART1_BCR] = { 0x1a000 },
3533 [GCC_BLSP1_QUP2_BCR] = { 0x1b000 },
3534 [GCC_BLSP1_UART2_BCR] = { 0x1c000 },
3535 [GCC_BLSP1_QUP3_BCR] = { 0x1d000 },
3536 [GCC_BLSP1_UART3_BCR] = { 0x1e000 },
3537 [GCC_BLSP1_QUP4_BCR] = { 0x1f000 },
3538 [GCC_BLSP1_UART4_BCR] = { 0x20000 },
3539 [GCC_BLSP1_QUP5_BCR] = { 0x21000 },
3540 [GCC_BLSP1_UART5_BCR] = { 0x22000 },
3541 [GCC_BLSP1_QUP6_BCR] = { 0x23000 },
3542 [GCC_BLSP1_UART6_BCR] = { 0x24000 },
3543 [GCC_BLSP2_BCR] = { 0x25000 },
3544 [GCC_BLSP2_QUP1_BCR] = { 0x26000 },
3545 [GCC_BLSP2_UART1_BCR] = { 0x27000 },
3546 [GCC_BLSP2_QUP2_BCR] = { 0x28000 },
3547 [GCC_BLSP2_UART2_BCR] = { 0x29000 },
3548 [GCC_BLSP2_QUP3_BCR] = { 0x2a000 },
3549 [GCC_BLSP2_UART3_BCR] = { 0x2b000 },
3550 [GCC_BLSP2_QUP4_BCR] = { 0x2c000 },
3551 [GCC_BLSP2_UART4_BCR] = { 0x2d000 },
3552 [GCC_BLSP2_QUP5_BCR] = { 0x2e000 },
3553 [GCC_BLSP2_UART5_BCR] = { 0x2f000 },
3554 [GCC_BLSP2_QUP6_BCR] = { 0x30000 },
3555 [GCC_BLSP2_UART6_BCR] = { 0x31000 },
3556 [GCC_PDM_BCR] = { 0x33000 },
3557 [GCC_PRNG_BCR] = { 0x34000 },
3558 [GCC_TSIF_BCR] = { 0x36000 },
3559 [GCC_TCSR_BCR] = { 0x37000 },
3560 [GCC_BOOT_ROM_BCR] = { 0x38000 },
3561 [GCC_MSG_RAM_BCR] = { 0x39000 },
3562 [GCC_TLMM_BCR] = { 0x3a000 },
3563 [GCC_MPM_BCR] = { 0x3b000 },
3564 [GCC_SEC_CTRL_BCR] = { 0x3d000 },
3565 [GCC_SPMI_BCR] = { 0x3f000 },
3566 [GCC_SPDM_BCR] = { 0x40000 },
3567 [GCC_CE1_BCR] = { 0x41000 },
3568 [GCC_BIMC_BCR] = { 0x44000 },
3569 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x49000 },
3570 [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x49008 },
3571 [GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x49010 },
3572 [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x49018 },
3573 [GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x49020 },
3574 [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x4a000 },
3575 [GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x4a008 },
3576 [GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x4a010 },
3577 [GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x4a018 },
3578 [GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x4a020 },
3579 [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x4b000 },
3580 [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x4b008 },
3581 [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x4b010 },
3582 [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x4b018 },
3583 [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x4b020 },
3584 [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x4b028 },
3585 [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x4b030 },
3586 [GCC_CNOC_BUS_TIMEOUT7_BCR] = { 0x4b038 },
3587 [GCC_CNOC_BUS_TIMEOUT8_BCR] = { 0x80000 },
3588 [GCC_CNOC_BUS_TIMEOUT9_BCR] = { 0x80008 },
3589 [GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x80010 },
3590 [GCC_APB2JTAG_BCR] = { 0x4c000 },
3591 [GCC_RBCPR_CX_BCR] = { 0x4e000 },
3592 [GCC_RBCPR_MX_BCR] = { 0x4f000 },
3593 [GCC_PCIE_0_BCR] = { 0x6b000 },
3594 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3595 [GCC_PCIE_1_BCR] = { 0x6d000 },
3596 [GCC_PCIE_1_PHY_BCR] = { 0x6d038 },
3597 [GCC_PCIE_2_BCR] = { 0x6e000 },
3598 [GCC_PCIE_2_PHY_BCR] = { 0x6e038 },
3599 [GCC_PCIE_PHY_BCR] = { 0x6f000 },
3600 [GCC_PCIE_PHY_COM_BCR] = { 0x6f014 },
3601 [GCC_PCIE_PHY_COM_NOCSR_BCR] = { 0x6f00c },
3602 [GCC_DCD_BCR] = { 0x70000 },
3603 [GCC_OBT_ODT_BCR] = { 0x73000 },
3604 [GCC_UFS_BCR] = { 0x75000 },
3605 [GCC_SSC_BCR] = { 0x63000 },
3606 [GCC_VS_BCR] = { 0x7a000 },
3607 [GCC_AGGRE0_NOC_BCR] = { 0x81000 },
3608 [GCC_AGGRE1_NOC_BCR] = { 0x82000 },
3609 [GCC_AGGRE2_NOC_BCR] = { 0x83000 },
3610 [GCC_DCC_BCR] = { 0x84000 },
3611 [GCC_IPA_BCR] = { 0x89000 },
3612 [GCC_QSPI_BCR] = { 0x8b000 },
3613 [GCC_SKL_BCR] = { 0x8c000 },
3614 [GCC_MSMPU_BCR] = { 0x8d000 },
3615 [GCC_MSS_Q6_BCR] = { 0x8e000 },
3616 [GCC_QREFS_VBG_CAL_BCR] = { 0x88020 },
3617 [GCC_MSS_RESTART] = { 0x8f008 },
3624 .max_register = 0x8f010,
3658 regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21)); in gcc_msm8996_probe()