Lines Matching +full:0 +full:x2c000
54 .l_reg = 0x21004,
55 .m_reg = 0x21008,
56 .n_reg = 0x2100c,
57 .config_reg = 0x21010,
58 .mode_reg = 0x21000,
59 .status_reg = 0x2101c,
72 .enable_reg = 0x45000,
73 .enable_mask = BIT(0),
85 .l_reg = 0x20004,
86 .m_reg = 0x20008,
87 .n_reg = 0x2000c,
88 .config_reg = 0x20010,
89 .mode_reg = 0x20000,
90 .status_reg = 0x2001c,
103 .enable_reg = 0x45000,
116 .l_reg = 0x4a004,
117 .m_reg = 0x4a008,
118 .n_reg = 0x4a00c,
119 .config_reg = 0x4a010,
120 .mode_reg = 0x4a000,
121 .status_reg = 0x4a01c,
134 .enable_reg = 0x45000,
147 .l_reg = 0x23004,
148 .m_reg = 0x23008,
149 .n_reg = 0x2300c,
150 .config_reg = 0x23010,
151 .mode_reg = 0x23000,
152 .status_reg = 0x2301c,
165 .enable_reg = 0x45000,
178 .l_reg = 0x22004,
179 .m_reg = 0x22008,
180 .n_reg = 0x2200c,
181 .config_reg = 0x22010,
182 .mode_reg = 0x22000,
183 .status_reg = 0x2201c,
196 .enable_reg = 0x45000,
213 .vco_val = 0x0,
215 .pre_div_val = 0x0,
217 .post_div_val = 0x0,
220 .main_output_mask = BIT(0),
225 .l_reg = 0x24004,
226 .m_reg = 0x24008,
227 .n_reg = 0x2400c,
228 .config_reg = 0x24010,
229 .mode_reg = 0x24000,
230 .status_reg = 0x2401c,
243 .enable_reg = 0x45000,
260 .vco_val = 0x0,
262 .pre_div_val = 0x0,
264 .post_div_val = 0x0,
267 .main_output_mask = BIT(0),
271 .l_reg = 0x25004,
272 .m_reg = 0x25008,
273 .n_reg = 0x2500c,
274 .config_reg = 0x25010,
275 .mode_reg = 0x25000,
276 .status_reg = 0x2501c,
289 .enable_reg = 0x45000,
302 .l_reg = 0x37004,
303 .m_reg = 0x37008,
304 .n_reg = 0x3700c,
305 .config_reg = 0x37010,
306 .mode_reg = 0x37000,
307 .status_reg = 0x3701c,
320 .enable_reg = 0x45000,
333 { P_XO, 0 },
343 { P_XO, 0 },
355 { P_XO, 0 },
367 { P_XO, 0 },
383 { P_XO, 0 },
395 { P_XO, 0 },
409 { P_XO, 0 },
419 { P_XO, 0 },
433 { P_XO, 0 },
449 { P_XO, 0 },
461 { P_XO, 0, },
471 { P_XO, 0 },
483 { P_XO, 0 },
501 { P_XO, 0 },
513 { P_XO, 0 },
529 { P_XO, 0 },
543 { P_XO, 0 },
559 { P_XO, 0 },
575 { P_XO, 0 },
585 { P_XO, 0 },
611 .cmd_rcgr = 0x27000,
623 .cmd_rcgr = 0x26004,
635 .cmd_rcgr = 0x32004,
649 F(80000000, P_GPLL0, 10, 0, 0),
654 .cmd_rcgr = 0x5a000,
668 F(19200000, P_XO, 1, 0, 0),
669 F(50000000, P_GPLL0, 16, 0, 0),
670 F(100000000, P_GPLL0, 8, 0, 0),
671 F(133330000, P_GPLL0, 6, 0, 0),
676 .cmd_rcgr = 0x46000,
689 F(100000000, P_GPLL0, 8, 0, 0),
690 F(200000000, P_GPLL0, 4, 0, 0),
695 .cmd_rcgr = 0x4e020,
708 .cmd_rcgr = 0x4f020,
721 F(19200000, P_XO, 1, 0, 0),
722 F(50000000, P_GPLL0, 16, 0, 0),
723 F(80000000, P_GPLL0, 10, 0, 0),
724 F(100000000, P_GPLL0, 8, 0, 0),
725 F(160000000, P_GPLL0, 5, 0, 0),
726 F(200000000, P_GPLL0, 4, 0, 0),
727 F(220000000, P_GPLL3, 5, 0, 0),
728 F(266670000, P_GPLL0, 3, 0, 0),
729 F(310000000, P_GPLL2_AUX, 3, 0, 0),
730 F(400000000, P_GPLL0, 2, 0, 0),
731 F(465000000, P_GPLL2_AUX, 2, 0, 0),
732 F(550000000, P_GPLL3, 2, 0, 0),
737 .cmd_rcgr = 0x59000,
750 F(50000000, P_GPLL0, 16, 0, 0),
751 F(80000000, P_GPLL0, 10, 0, 0),
752 F(100000000, P_GPLL0, 8, 0, 0),
753 F(160000000, P_GPLL0, 5, 0, 0),
754 F(177780000, P_GPLL0, 4.5, 0, 0),
755 F(200000000, P_GPLL0, 4, 0, 0),
756 F(266670000, P_GPLL0, 3, 0, 0),
757 F(320000000, P_GPLL0, 2.5, 0, 0),
758 F(400000000, P_GPLL0, 2, 0, 0),
759 F(465000000, P_GPLL2, 2, 0, 0),
760 F(480000000, P_GPLL4, 2.5, 0, 0),
761 F(600000000, P_GPLL4, 2, 0, 0),
766 .cmd_rcgr = 0x58000,
779 F(19200000, P_XO, 1, 0, 0),
780 F(50000000, P_GPLL0, 16, 0, 0),
785 .cmd_rcgr = 0x0200c,
799 F(4800000, P_XO, 4, 0, 0),
800 F(9600000, P_XO, 2, 0, 0),
802 F(19200000, P_XO, 1, 0, 0),
804 F(50000000, P_GPLL0, 16, 0, 0),
809 .cmd_rcgr = 0x02024,
823 .cmd_rcgr = 0x03000,
836 .cmd_rcgr = 0x03014,
850 .cmd_rcgr = 0x04000,
863 .cmd_rcgr = 0x04024,
877 .cmd_rcgr = 0x05000,
890 .cmd_rcgr = 0x05024,
904 .cmd_rcgr = 0x06000,
917 .cmd_rcgr = 0x06024,
931 .cmd_rcgr = 0x07000,
944 .cmd_rcgr = 0x07024,
962 F(19200000, P_XO, 1, 0, 0),
977 .cmd_rcgr = 0x02044,
991 .cmd_rcgr = 0x03034,
1005 F(19200000, P_XO, 1, 0, 0),
1010 .cmd_rcgr = 0x51000,
1024 F(100000000, P_GPLL0, 8, 0, 0),
1025 F(200000000, P_GPLL0, 4, 0, 0),
1030 .cmd_rcgr = 0x54000,
1044 .cmd_rcgr = 0x55000,
1058 F(133330000, P_GPLL0, 6, 0, 0),
1059 F(266670000, P_GPLL0, 3, 0, 0),
1060 F(320000000, P_GPLL0, 2.5, 0, 0),
1065 .cmd_rcgr = 0x57000,
1079 F(66670000, P_GPLL0, 12, 0, 0),
1084 .cmd_rcgr = 0x52000,
1098 .cmd_rcgr = 0x53000,
1112 F(100000000, P_GPLL0, 8, 0, 0),
1113 F(200000000, P_GPLL0, 4, 0, 0),
1118 .cmd_rcgr = 0x4e000,
1131 .cmd_rcgr = 0x4f000,
1144 F(160000000, P_GPLL0, 5, 0, 0),
1145 F(320000000, P_GPLL0, 2.5, 0, 0),
1146 F(465000000, P_GPLL2, 2, 0, 0),
1151 .cmd_rcgr = 0x58018,
1164 F(50000000, P_GPLL0, 16, 0, 0),
1165 F(80000000, P_GPLL0, 10, 0, 0),
1166 F(100000000, P_GPLL0, 8, 0, 0),
1167 F(160000000, P_GPLL0, 5, 0, 0),
1173 .cmd_rcgr = 0x16004,
1186 F(19200000, P_XO, 1, 0, 0),
1191 .cmd_rcgr = 0x08004,
1205 .cmd_rcgr = 0x09004,
1219 .cmd_rcgr = 0x0a004,
1233 .cmd_rcgr = 0x4d044,
1246 .cmd_rcgr = 0x4d0b0,
1259 F(19200000, P_XO, 1, 0, 0),
1264 .cmd_rcgr = 0x4d060,
1277 .cmd_rcgr = 0x4d0a8,
1290 F(50000000, P_GPLL0_AUX, 16, 0, 0),
1291 F(80000000, P_GPLL0_AUX, 10, 0, 0),
1292 F(100000000, P_GPLL0_AUX, 8, 0, 0),
1293 F(160000000, P_GPLL0_AUX, 5, 0, 0),
1294 F(177780000, P_GPLL0_AUX, 4.5, 0, 0),
1295 F(200000000, P_GPLL0_AUX, 4, 0, 0),
1296 F(266670000, P_GPLL0_AUX, 3, 0, 0),
1297 F(307200000, P_GPLL1, 2, 0, 0),
1298 F(366670000, P_GPLL3_AUX, 3, 0, 0),
1303 .cmd_rcgr = 0x4d014,
1316 .cmd_rcgr = 0x4d000,
1330 .cmd_rcgr = 0x4d0b8,
1344 F(19200000, P_XO, 1, 0, 0),
1349 .cmd_rcgr = 0x4d02c,
1362 F(64000000, P_GPLL0, 12.5, 0, 0),
1368 .cmd_rcgr = 0x44010,
1385 F(50000000, P_GPLL0, 16, 0, 0),
1386 F(100000000, P_GPLL0, 8, 0, 0),
1387 F(177770000, P_GPLL0, 4.5, 0, 0),
1388 F(200000000, P_GPLL0, 4, 0, 0),
1393 .cmd_rcgr = 0x42004,
1407 .cmd_rcgr = 0x43004,
1421 F(154285000, P_GPLL6, 7, 0, 0),
1422 F(320000000, P_GPLL0, 2.5, 0, 0),
1423 F(400000000, P_GPLL0, 2, 0, 0),
1428 .cmd_rcgr = 0x1207c,
1441 F(19200000, P_XO, 1, 0, 0),
1442 F(100000000, P_GPLL0, 8, 0, 0),
1443 F(200000000, P_GPLL0, 4, 0, 0),
1444 F(266500000, P_BIMC, 4, 0, 0),
1445 F(400000000, P_GPLL0, 2, 0, 0),
1446 F(533000000, P_BIMC, 2, 0, 0),
1451 .cmd_rcgr = 0x31028,
1465 F(80000000, P_GPLL0, 10, 0, 0),
1470 .cmd_rcgr = 0x41010,
1483 F(64000000, P_GPLL0, 12.5, 0, 0),
1488 .cmd_rcgr = 0x3f010,
1506 .cmd_rcgr = 0x3f034,
1519 F(3200000, P_XO, 6, 0, 0),
1520 F(6400000, P_XO, 3, 0, 0),
1521 F(9600000, P_XO, 2, 0, 0),
1522 F(19200000, P_XO, 1, 0, 0),
1524 F(66670000, P_GPLL0, 12, 0, 0),
1525 F(80000000, P_GPLL0, 10, 0, 0),
1526 F(100000000, P_GPLL0, 8, 0, 0),
1531 .cmd_rcgr = 0x1c010,
1545 .halt_reg = 0x1c028,
1547 .enable_reg = 0x1c028,
1548 .enable_mask = BIT(0),
1562 .halt_reg = 0x1c024,
1564 .enable_reg = 0x1c024,
1565 .enable_mask = BIT(0),
1591 F(1600000, P_XO, 12, 0, 0),
1595 F(2400000, P_XO, 8, 0, 0),
1599 F(4800000, P_XO, 4, 0, 0),
1603 F(9600000, P_XO, 2, 0, 0),
1610 .cmd_rcgr = 0x1c054,
1624 .halt_reg = 0x1c068,
1626 .enable_reg = 0x1c068,
1627 .enable_mask = BIT(0),
1641 .cmd_rcgr = 0x1c06c,
1655 .halt_reg = 0x1c080,
1657 .enable_reg = 0x1c080,
1658 .enable_mask = BIT(0),
1672 .cmd_rcgr = 0x1c084,
1686 .halt_reg = 0x1c098,
1688 .enable_reg = 0x1c098,
1689 .enable_mask = BIT(0),
1703 F(19200000, P_XO, 1, 0, 0),
1708 .cmd_rcgr = 0x1c034,
1721 .halt_reg = 0x1c04c,
1723 .enable_reg = 0x1c04c,
1724 .enable_mask = BIT(0),
1738 .halt_reg = 0x1c050,
1740 .enable_reg = 0x1c050,
1741 .enable_mask = BIT(0),
1755 F(9600000, P_XO, 2, 0, 0),
1757 F(19200000, P_XO, 1, 0, 0),
1758 F(11289600, P_EXT_MCLK, 1, 0, 0),
1763 .cmd_rcgr = 0x1c09c,
1777 .halt_reg = 0x1c0b0,
1779 .enable_reg = 0x1c0b0,
1780 .enable_mask = BIT(0),
1794 .halt_reg = 0x1c000,
1796 .enable_reg = 0x1c000,
1797 .enable_mask = BIT(0),
1810 .halt_reg = 0x1c004,
1812 .enable_reg = 0x1c004,
1813 .enable_mask = BIT(0),
1826 F(100000000, P_GPLL0, 8, 0, 0),
1827 F(160000000, P_GPLL0, 5, 0, 0),
1828 F(228570000, P_GPLL0, 3.5, 0, 0),
1833 .cmd_rcgr = 0x4C000,
1847 .halt_reg = 0x01008,
1850 .enable_reg = 0x45004,
1864 .halt_reg = 0x01004,
1866 .enable_reg = 0x01004,
1867 .enable_mask = BIT(0),
1876 .halt_reg = 0x02008,
1878 .enable_reg = 0x02008,
1879 .enable_mask = BIT(0),
1893 .halt_reg = 0x02004,
1895 .enable_reg = 0x02004,
1896 .enable_mask = BIT(0),
1910 .halt_reg = 0x03010,
1912 .enable_reg = 0x03010,
1913 .enable_mask = BIT(0),
1927 .halt_reg = 0x0300c,
1929 .enable_reg = 0x0300c,
1930 .enable_mask = BIT(0),
1944 .halt_reg = 0x04020,
1946 .enable_reg = 0x04020,
1947 .enable_mask = BIT(0),
1961 .halt_reg = 0x0401c,
1963 .enable_reg = 0x0401c,
1964 .enable_mask = BIT(0),
1978 .halt_reg = 0x05020,
1980 .enable_reg = 0x05020,
1981 .enable_mask = BIT(0),
1995 .halt_reg = 0x0501c,
1997 .enable_reg = 0x0501c,
1998 .enable_mask = BIT(0),
2012 .halt_reg = 0x06020,
2014 .enable_reg = 0x06020,
2015 .enable_mask = BIT(0),
2029 .halt_reg = 0x0601c,
2031 .enable_reg = 0x0601c,
2032 .enable_mask = BIT(0),
2046 .halt_reg = 0x07020,
2048 .enable_reg = 0x07020,
2049 .enable_mask = BIT(0),
2063 .halt_reg = 0x0701c,
2065 .enable_reg = 0x0701c,
2066 .enable_mask = BIT(0),
2080 .halt_reg = 0x0203c,
2082 .enable_reg = 0x0203c,
2083 .enable_mask = BIT(0),
2097 .halt_reg = 0x0302c,
2099 .enable_reg = 0x0302c,
2100 .enable_mask = BIT(0),
2114 .halt_reg = 0x1300c,
2117 .enable_reg = 0x45004,
2131 .halt_reg = 0x5101c,
2133 .enable_reg = 0x5101c,
2134 .enable_mask = BIT(0),
2148 .halt_reg = 0x51018,
2150 .enable_reg = 0x51018,
2151 .enable_mask = BIT(0),
2165 .halt_reg = 0x4e040,
2167 .enable_reg = 0x4e040,
2168 .enable_mask = BIT(0),
2182 .halt_reg = 0x4e03c,
2184 .enable_reg = 0x4e03c,
2185 .enable_mask = BIT(0),
2199 .halt_reg = 0x4e048,
2201 .enable_reg = 0x4e048,
2202 .enable_mask = BIT(0),
2216 .halt_reg = 0x4e058,
2218 .enable_reg = 0x4e058,
2219 .enable_mask = BIT(0),
2233 .halt_reg = 0x4e050,
2235 .enable_reg = 0x4e050,
2236 .enable_mask = BIT(0),
2250 .halt_reg = 0x4f040,
2252 .enable_reg = 0x4f040,
2253 .enable_mask = BIT(0),
2267 .halt_reg = 0x4f03c,
2269 .enable_reg = 0x4f03c,
2270 .enable_mask = BIT(0),
2284 .halt_reg = 0x4f048,
2286 .enable_reg = 0x4f048,
2287 .enable_mask = BIT(0),
2301 .halt_reg = 0x4f058,
2303 .enable_reg = 0x4f058,
2304 .enable_mask = BIT(0),
2318 .halt_reg = 0x4f050,
2320 .enable_reg = 0x4f050,
2321 .enable_mask = BIT(0),
2335 .halt_reg = 0x58050,
2337 .enable_reg = 0x58050,
2338 .enable_mask = BIT(0),
2352 .halt_reg = 0x54018,
2354 .enable_reg = 0x54018,
2355 .enable_mask = BIT(0),
2369 .halt_reg = 0x55018,
2371 .enable_reg = 0x55018,
2372 .enable_mask = BIT(0),
2386 .halt_reg = 0x50004,
2388 .enable_reg = 0x50004,
2389 .enable_mask = BIT(0),
2403 .halt_reg = 0x57020,
2405 .enable_reg = 0x57020,
2406 .enable_mask = BIT(0),
2420 .halt_reg = 0x57024,
2422 .enable_reg = 0x57024,
2423 .enable_mask = BIT(0),
2437 .halt_reg = 0x57028,
2439 .enable_reg = 0x57028,
2440 .enable_mask = BIT(0),
2454 .halt_reg = 0x52018,
2456 .enable_reg = 0x52018,
2457 .enable_mask = BIT(0),
2471 .halt_reg = 0x53018,
2473 .enable_reg = 0x53018,
2474 .enable_mask = BIT(0),
2488 .halt_reg = 0x5600c,
2490 .enable_reg = 0x5600c,
2491 .enable_mask = BIT(0),
2505 .halt_reg = 0x4e01c,
2507 .enable_reg = 0x4e01c,
2508 .enable_mask = BIT(0),
2522 .halt_reg = 0x4f01c,
2524 .enable_reg = 0x4f01c,
2525 .enable_mask = BIT(0),
2539 .halt_reg = 0x5a014,
2541 .enable_reg = 0x5a014,
2542 .enable_mask = BIT(0),
2556 .halt_reg = 0x56004,
2558 .enable_reg = 0x56004,
2559 .enable_mask = BIT(0),
2573 .halt_reg = 0x58040,
2575 .enable_reg = 0x58040,
2576 .enable_mask = BIT(0),
2590 .halt_reg = 0x5803c,
2592 .enable_reg = 0x5803c,
2593 .enable_mask = BIT(0),
2607 .halt_reg = 0x58038,
2609 .enable_reg = 0x58038,
2610 .enable_mask = BIT(0),
2624 .halt_reg = 0x58044,
2626 .enable_reg = 0x58044,
2627 .enable_mask = BIT(0),
2641 .halt_reg = 0x58048,
2643 .enable_reg = 0x58048,
2644 .enable_mask = BIT(0),
2658 .halt_reg = 0x16024,
2661 .enable_reg = 0x45004,
2662 .enable_mask = BIT(0),
2676 .halt_reg = 0x16020,
2679 .enable_reg = 0x45004,
2694 .halt_reg = 0x1601c,
2697 .enable_reg = 0x45004,
2712 .halt_reg = 0x59024,
2714 .enable_reg = 0x59024,
2715 .enable_mask = BIT(0),
2729 .halt_reg = 0x08000,
2731 .enable_reg = 0x08000,
2732 .enable_mask = BIT(0),
2746 .halt_reg = 0x09000,
2748 .enable_reg = 0x09000,
2749 .enable_mask = BIT(0),
2763 .halt_reg = 0x0a000,
2765 .enable_reg = 0x0a000,
2766 .enable_mask = BIT(0),
2780 .halt_reg = 0x4d07c,
2782 .enable_reg = 0x4d07c,
2783 .enable_mask = BIT(0),
2797 .halt_reg = 0x4d080,
2799 .enable_reg = 0x4d080,
2800 .enable_mask = BIT(0),
2814 .halt_reg = 0x4d094,
2816 .enable_reg = 0x4d094,
2817 .enable_mask = BIT(0),
2831 .halt_reg = 0x4d0a0,
2833 .enable_reg = 0x4d0a0,
2834 .enable_mask = BIT(0),
2848 .halt_reg = 0x4d098,
2850 .enable_reg = 0x4d098,
2851 .enable_mask = BIT(0),
2865 .halt_reg = 0x4d09c,
2867 .enable_reg = 0x4d09c,
2868 .enable_mask = BIT(0),
2882 .halt_reg = 0x4D088,
2884 .enable_reg = 0x4D088,
2885 .enable_mask = BIT(0),
2899 .halt_reg = 0x4d084,
2901 .enable_reg = 0x4d084,
2902 .enable_mask = BIT(0),
2916 .halt_reg = 0x4d0a4,
2918 .enable_reg = 0x4d0a4,
2919 .enable_mask = BIT(0),
2933 .halt_reg = 0x4d090,
2935 .enable_reg = 0x4d090,
2936 .enable_mask = BIT(0),
2950 .halt_reg = 0x49000,
2952 .enable_reg = 0x49000,
2953 .enable_mask = BIT(0),
2967 .halt_reg = 0x49004,
2969 .enable_reg = 0x49004,
2970 .enable_mask = BIT(0),
2984 .halt_reg = 0x59028,
2986 .enable_reg = 0x59028,
2987 .enable_mask = BIT(0),
3001 .halt_reg = 0x59020,
3003 .enable_reg = 0x59020,
3004 .enable_mask = BIT(0),
3018 .halt_reg = 0x4400c,
3020 .enable_reg = 0x4400c,
3021 .enable_mask = BIT(0),
3035 .halt_reg = 0x44004,
3037 .enable_reg = 0x44004,
3038 .enable_mask = BIT(0),
3052 .halt_reg = 0x13004,
3055 .enable_reg = 0x45004,
3069 .halt_reg = 0x4201c,
3071 .enable_reg = 0x4201c,
3072 .enable_mask = BIT(0),
3086 .halt_reg = 0x42018,
3088 .enable_reg = 0x42018,
3089 .enable_mask = BIT(0),
3103 .halt_reg = 0x4301c,
3105 .enable_reg = 0x4301c,
3106 .enable_mask = BIT(0),
3120 .halt_reg = 0x43018,
3122 .enable_reg = 0x43018,
3123 .enable_mask = BIT(0),
3137 .halt_reg = 0x12018,
3140 .enable_reg = 0x4500c,
3154 .halt_reg = 0x12020,
3157 .enable_reg = 0x4500c,
3171 .halt_reg = 0x12010,
3174 .enable_reg = 0x4500c,
3188 .halt_reg = 0x1201c,
3191 .enable_reg = 0x4500c,
3206 .halt_reg = 0x12014,
3209 .enable_reg = 0x4500c,
3224 .halt_reg = 0x1203c,
3227 .enable_reg = 0x4500c,
3242 .halt_reg = 0x12034,
3245 .enable_reg = 0x4500c,
3260 .halt_reg = 0x12038,
3263 .enable_reg = 0x4500c,
3278 .halt_reg = 0x12044,
3281 .enable_reg = 0x4500c,
3296 .halt_reg = 0x12040,
3299 .enable_reg = 0x4500c,
3314 .halt_reg = 0x1201c,
3317 .enable_reg = 0x4500c,
3332 .halt_reg = 0x31024,
3334 .enable_reg = 0x31024,
3335 .enable_mask = BIT(0),
3349 .halt_reg = 0x31040,
3351 .enable_reg = 0x31040,
3352 .enable_mask = BIT(0),
3366 .halt_reg = 0x4102c,
3368 .enable_reg = 0x4102c,
3369 .enable_mask = BIT(0),
3378 .halt_reg = 0x3f008,
3380 .enable_reg = 0x3f008,
3381 .enable_mask = BIT(0),
3395 .halt_reg = 0x3f030,
3397 .enable_reg = 0x3f030,
3398 .enable_mask = BIT(0),
3412 .halt_reg = 0x3f004,
3414 .enable_reg = 0x3f004,
3415 .enable_mask = BIT(0),
3429 .halt_reg = 0x41008,
3431 .enable_reg = 0x41008,
3432 .enable_mask = BIT(0),
3446 .halt_reg = 0x41004,
3448 .enable_reg = 0x41004,
3449 .enable_mask = BIT(0),
3463 .halt_reg = 0x4c020,
3465 .enable_reg = 0x4c020,
3466 .enable_mask = BIT(0),
3480 .halt_reg = 0x4c024,
3482 .enable_reg = 0x4c024,
3483 .enable_mask = BIT(0),
3497 .halt_reg = 0x4c01c,
3499 .enable_reg = 0x4c01c,
3500 .enable_mask = BIT(0),
3514 .halt_reg = 0x4c02c,
3516 .enable_reg = 0x4c02c,
3517 .enable_mask = BIT(0),
3531 .halt_reg = 0x4c034,
3533 .enable_reg = 0x4c034,
3534 .enable_mask = BIT(0),
3548 .halt_reg = 0x59040,
3550 .enable_reg = 0x59040,
3551 .enable_mask = BIT(0),
3560 .gdscr = 0x4c018,
3568 .gdscr = 0x4d078,
3576 .gdscr = 0x5701c,
3584 .gdscr = 0x58034,
3592 .gdscr = 0x5901c,
3600 .gdscr = 0x4c028,
3608 .gdscr = 0x4c030,
3815 [GCC_BLSP1_BCR] = { 0x01000 },
3816 [GCC_BLSP1_QUP1_BCR] = { 0x02000 },
3817 [GCC_BLSP1_UART1_BCR] = { 0x02038 },
3818 [GCC_BLSP1_QUP2_BCR] = { 0x03008 },
3819 [GCC_BLSP1_UART2_BCR] = { 0x03028 },
3820 [GCC_BLSP1_QUP3_BCR] = { 0x04018 },
3821 [GCC_BLSP1_UART3_BCR] = { 0x04038 },
3822 [GCC_BLSP1_QUP4_BCR] = { 0x05018 },
3823 [GCC_BLSP1_QUP5_BCR] = { 0x06018 },
3824 [GCC_BLSP1_QUP6_BCR] = { 0x07018 },
3825 [GCC_IMEM_BCR] = { 0x0e000 },
3826 [GCC_SMMU_BCR] = { 0x12000 },
3827 [GCC_APSS_TCU_BCR] = { 0x12050 },
3828 [GCC_SMMU_XPU_BCR] = { 0x12054 },
3829 [GCC_PCNOC_TBU_BCR] = { 0x12058 },
3830 [GCC_PRNG_BCR] = { 0x13000 },
3831 [GCC_BOOT_ROM_BCR] = { 0x13008 },
3832 [GCC_CRYPTO_BCR] = { 0x16000 },
3833 [GCC_SEC_CTRL_BCR] = { 0x1a000 },
3834 [GCC_AUDIO_CORE_BCR] = { 0x1c008 },
3835 [GCC_ULT_AUDIO_BCR] = { 0x1c0b4 },
3836 [GCC_DEHR_BCR] = { 0x1f000 },
3837 [GCC_SYSTEM_NOC_BCR] = { 0x26000 },
3838 [GCC_PCNOC_BCR] = { 0x27018 },
3839 [GCC_TCSR_BCR] = { 0x28000 },
3840 [GCC_QDSS_BCR] = { 0x29000 },
3841 [GCC_DCD_BCR] = { 0x2a000 },
3842 [GCC_MSG_RAM_BCR] = { 0x2b000 },
3843 [GCC_MPM_BCR] = { 0x2c000 },
3844 [GCC_SPMI_BCR] = { 0x2e000 },
3845 [GCC_SPDM_BCR] = { 0x2f000 },
3846 [GCC_MM_SPDM_BCR] = { 0x2f024 },
3847 [GCC_BIMC_BCR] = { 0x31000 },
3848 [GCC_RBCPR_BCR] = { 0x33000 },
3849 [GCC_TLMM_BCR] = { 0x34000 },
3850 [GCC_CAMSS_CSI2_BCR] = { 0x3c038 },
3851 [GCC_CAMSS_CSI2PHY_BCR] = { 0x3c044 },
3852 [GCC_CAMSS_CSI2RDI_BCR] = { 0x3c04c },
3853 [GCC_CAMSS_CSI2PIX_BCR] = { 0x3c054 },
3854 [GCC_USB_FS_BCR] = { 0x3f000 },
3855 [GCC_USB_HS_BCR] = { 0x41000 },
3856 [GCC_USB2A_PHY_BCR] = { 0x41028 },
3857 [GCC_SDCC1_BCR] = { 0x42000 },
3858 [GCC_SDCC2_BCR] = { 0x43000 },
3859 [GCC_PDM_BCR] = { 0x44000 },
3860 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000 },
3861 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000 },
3862 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008 },
3863 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010 },
3864 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018 },
3865 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020 },
3866 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028 },
3867 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030 },
3868 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038 },
3869 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040 },
3870 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048 },
3871 [GCC_MMSS_BCR] = { 0x4b000 },
3872 [GCC_VENUS0_BCR] = { 0x4c014 },
3873 [GCC_MDSS_BCR] = { 0x4d074 },
3874 [GCC_CAMSS_PHY0_BCR] = { 0x4e018 },
3875 [GCC_CAMSS_CSI0_BCR] = { 0x4e038 },
3876 [GCC_CAMSS_CSI0PHY_BCR] = { 0x4e044 },
3877 [GCC_CAMSS_CSI0RDI_BCR] = { 0x4e04c },
3878 [GCC_CAMSS_CSI0PIX_BCR] = { 0x4e054 },
3879 [GCC_CAMSS_PHY1_BCR] = { 0x4f018 },
3880 [GCC_CAMSS_CSI1_BCR] = { 0x4f038 },
3881 [GCC_CAMSS_CSI1PHY_BCR] = { 0x4f044 },
3882 [GCC_CAMSS_CSI1RDI_BCR] = { 0x4f04c },
3883 [GCC_CAMSS_CSI1PIX_BCR] = { 0x4f054 },
3884 [GCC_CAMSS_ISPIF_BCR] = { 0x50000 },
3885 [GCC_BLSP1_QUP4_SPI_APPS_CBCR] = { 0x0501c },
3886 [GCC_CAMSS_CCI_BCR] = { 0x51014 },
3887 [GCC_CAMSS_MCLK0_BCR] = { 0x52014 },
3888 [GCC_CAMSS_MCLK1_BCR] = { 0x53014 },
3889 [GCC_CAMSS_GP0_BCR] = { 0x54014 },
3890 [GCC_CAMSS_GP1_BCR] = { 0x55014 },
3891 [GCC_CAMSS_TOP_BCR] = { 0x56000 },
3892 [GCC_CAMSS_MICRO_BCR] = { 0x56008 },
3893 [GCC_CAMSS_JPEG_BCR] = { 0x57018 },
3894 [GCC_CAMSS_VFE_BCR] = { 0x58030 },
3895 [GCC_CAMSS_CSI_VFE0_BCR] = { 0x5804c },
3896 [GCC_OXILI_BCR] = { 0x59018 },
3897 [GCC_GMEM_BCR] = { 0x5902c },
3898 [GCC_CAMSS_AHB_BCR] = { 0x5a018 },
3899 [GCC_CAMSS_MCLK2_BCR] = { 0x5c014 },
3900 [GCC_MDP_TBU_BCR] = { 0x62000 },
3901 [GCC_GFX_TBU_BCR] = { 0x63000 },
3902 [GCC_GFX_TCU_BCR] = { 0x64000 },
3903 [GCC_MSS_TBU_AXI_BCR] = { 0x65000 },
3904 [GCC_MSS_TBU_GSS_AXI_BCR] = { 0x66000 },
3905 [GCC_MSS_TBU_Q6_AXI_BCR] = { 0x67000 },
3906 [GCC_GTCU_AHB_BCR] = { 0x68000 },
3907 [GCC_SMMU_CFG_BCR] = { 0x69000 },
3908 [GCC_VFE_TBU_BCR] = { 0x6a000 },
3909 [GCC_VENUS_TBU_BCR] = { 0x6b000 },
3910 [GCC_JPEG_TBU_BCR] = { 0x6c000 },
3911 [GCC_PRONTO_TBU_BCR] = { 0x6d000 },
3912 [GCC_CPP_TBU_BCR] = { 0x6e000 },
3913 [GCC_MDP_RT_TBU_BCR] = { 0x6f000 },
3914 [GCC_SMMU_CATS_BCR] = { 0x7c000 },
3921 .max_register = 0x80000,