Lines Matching +full:0 +full:x2c000
46 { P_XO, 0 },
56 { P_XO, 0 },
68 { P_XO, 0 },
82 { P_XO, 0 },
94 { P_XO, 0 },
104 { P_XO, 0 },
118 { P_XO, 0 },
130 { P_XO, 0, },
140 { P_XO, 0 },
152 { P_XO, 0 },
164 { P_XO, 0 },
176 { P_XO, 0 },
190 { P_XO, 0 },
204 { P_XO, 0 },
220 { P_XO, 0 },
236 { P_XO, 0 },
246 { P_XO, 0 },
260 .l_reg = 0x21004,
261 .m_reg = 0x21008,
262 .n_reg = 0x2100c,
263 .config_reg = 0x21010,
264 .mode_reg = 0x21000,
265 .status_reg = 0x2101c,
276 .enable_reg = 0x45000,
277 .enable_mask = BIT(0),
287 .l_reg = 0x20004,
288 .m_reg = 0x20008,
289 .n_reg = 0x2000c,
290 .config_reg = 0x20010,
291 .mode_reg = 0x20000,
292 .status_reg = 0x2001c,
303 .enable_reg = 0x45000,
314 .l_reg = 0x4a004,
315 .m_reg = 0x4a008,
316 .n_reg = 0x4a00c,
317 .config_reg = 0x4a010,
318 .mode_reg = 0x4a000,
319 .status_reg = 0x4a01c,
330 .enable_reg = 0x45000,
341 .l_reg = 0x23004,
342 .m_reg = 0x23008,
343 .n_reg = 0x2300c,
344 .config_reg = 0x23010,
345 .mode_reg = 0x23000,
346 .status_reg = 0x2301c,
357 .enable_reg = 0x45000,
368 .cmd_rcgr = 0x27000,
380 .cmd_rcgr = 0x26004,
393 F(80000000, P_GPLL0, 10, 0, 0),
398 .cmd_rcgr = 0x5a000,
412 F(19200000, P_XO, 1, 0, 0),
413 F(50000000, P_GPLL0, 16, 0, 0),
414 F(100000000, P_GPLL0, 8, 0, 0),
415 F(133330000, P_GPLL0, 6, 0, 0),
420 .cmd_rcgr = 0x46000,
433 F(100000000, P_GPLL0, 8, 0, 0),
434 F(200000000, P_GPLL0, 4, 0, 0),
439 .cmd_rcgr = 0x4e020,
452 .cmd_rcgr = 0x4f020,
465 F(19200000, P_XO, 1, 0, 0),
466 F(50000000, P_GPLL0_AUX, 16, 0, 0),
467 F(80000000, P_GPLL0_AUX, 10, 0, 0),
468 F(100000000, P_GPLL0_AUX, 8, 0, 0),
469 F(160000000, P_GPLL0_AUX, 5, 0, 0),
470 F(177780000, P_GPLL0_AUX, 4.5, 0, 0),
471 F(200000000, P_GPLL0_AUX, 4, 0, 0),
472 F(266670000, P_GPLL0_AUX, 3, 0, 0),
473 F(294912000, P_GPLL1, 3, 0, 0),
474 F(310000000, P_GPLL2, 3, 0, 0),
475 F(400000000, P_GPLL0_AUX, 2, 0, 0),
480 .cmd_rcgr = 0x59000,
493 F(50000000, P_GPLL0, 16, 0, 0),
494 F(80000000, P_GPLL0, 10, 0, 0),
495 F(100000000, P_GPLL0, 8, 0, 0),
496 F(160000000, P_GPLL0, 5, 0, 0),
497 F(177780000, P_GPLL0, 4.5, 0, 0),
498 F(200000000, P_GPLL0, 4, 0, 0),
499 F(266670000, P_GPLL0, 3, 0, 0),
500 F(320000000, P_GPLL0, 2.5, 0, 0),
501 F(400000000, P_GPLL0, 2, 0, 0),
502 F(465000000, P_GPLL2, 2, 0, 0),
507 .cmd_rcgr = 0x58000,
520 F(19200000, P_XO, 1, 0, 0),
521 F(50000000, P_GPLL0, 16, 0, 0),
526 .cmd_rcgr = 0x0200c,
544 F(4800000, P_XO, 4, 0, 0),
545 F(9600000, P_XO, 2, 0, 0),
547 F(19200000, P_XO, 1, 0, 0),
549 F(50000000, P_GPLL0, 16, 0, 0),
554 .cmd_rcgr = 0x02024,
568 .cmd_rcgr = 0x03000,
581 .cmd_rcgr = 0x03014,
595 .cmd_rcgr = 0x04000,
608 .cmd_rcgr = 0x04024,
622 .cmd_rcgr = 0x05000,
635 .cmd_rcgr = 0x05024,
649 .cmd_rcgr = 0x06000,
662 .cmd_rcgr = 0x06024,
676 .cmd_rcgr = 0x07000,
689 .cmd_rcgr = 0x07024,
707 F(19200000, P_XO, 1, 0, 0),
722 .cmd_rcgr = 0x02044,
736 .cmd_rcgr = 0x03034,
750 F(19200000, P_XO, 1, 0, 0),
755 .cmd_rcgr = 0x51000,
769 F(100000000, P_GPLL0, 8, 0, 0),
770 F(200000000, P_GPLL0, 4, 0, 0),
775 .cmd_rcgr = 0x54000,
789 .cmd_rcgr = 0x55000,
803 F(133330000, P_GPLL0, 6, 0, 0),
804 F(266670000, P_GPLL0, 3, 0, 0),
805 F(320000000, P_GPLL0, 2.5, 0, 0),
810 .cmd_rcgr = 0x57000,
823 F(9600000, P_XO, 2, 0, 0),
825 F(66670000, P_GPLL0, 12, 0, 0),
830 .cmd_rcgr = 0x52000,
844 .cmd_rcgr = 0x53000,
858 F(100000000, P_GPLL0, 8, 0, 0),
859 F(200000000, P_GPLL0, 4, 0, 0),
864 .cmd_rcgr = 0x4e000,
877 .cmd_rcgr = 0x4f000,
890 F(160000000, P_GPLL0, 5, 0, 0),
891 F(320000000, P_GPLL0, 2.5, 0, 0),
892 F(465000000, P_GPLL2, 2, 0, 0),
897 .cmd_rcgr = 0x58018,
910 F(50000000, P_GPLL0, 16, 0, 0),
911 F(80000000, P_GPLL0, 10, 0, 0),
912 F(100000000, P_GPLL0, 8, 0, 0),
913 F(160000000, P_GPLL0, 5, 0, 0),
918 .cmd_rcgr = 0x16004,
931 F(19200000, P_XO, 1, 0, 0),
936 .cmd_rcgr = 0x08004,
950 .cmd_rcgr = 0x09004,
964 .cmd_rcgr = 0x0a004,
978 .cmd_rcgr = 0x4d044,
991 F(19200000, P_XO, 1, 0, 0),
996 .cmd_rcgr = 0x4d05c,
1009 F(50000000, P_GPLL0, 16, 0, 0),
1010 F(80000000, P_GPLL0, 10, 0, 0),
1011 F(100000000, P_GPLL0, 8, 0, 0),
1012 F(160000000, P_GPLL0, 5, 0, 0),
1013 F(177780000, P_GPLL0, 4.5, 0, 0),
1014 F(200000000, P_GPLL0, 4, 0, 0),
1015 F(266670000, P_GPLL0, 3, 0, 0),
1016 F(320000000, P_GPLL0, 2.5, 0, 0),
1021 .cmd_rcgr = 0x4d014,
1034 .cmd_rcgr = 0x4d000,
1048 F(19200000, P_XO, 1, 0, 0),
1053 .cmd_rcgr = 0x4d02c,
1066 F(64000000, P_GPLL0, 12.5, 0, 0),
1071 .cmd_rcgr = 0x44010,
1088 F(50000000, P_GPLL0, 16, 0, 0),
1089 F(100000000, P_GPLL0, 8, 0, 0),
1090 F(177770000, P_GPLL0, 4.5, 0, 0),
1095 .cmd_rcgr = 0x42004,
1113 F(50000000, P_GPLL0, 16, 0, 0),
1114 F(100000000, P_GPLL0, 8, 0, 0),
1115 F(200000000, P_GPLL0, 4, 0, 0),
1120 .cmd_rcgr = 0x43004,
1134 F(155000000, P_GPLL2, 6, 0, 0),
1135 F(310000000, P_GPLL2, 3, 0, 0),
1136 F(400000000, P_GPLL0, 2, 0, 0),
1141 .cmd_rcgr = 0x1207c,
1154 F(19200000, P_XO, 1, 0, 0),
1155 F(100000000, P_GPLL0, 8, 0, 0),
1156 F(200000000, P_GPLL0, 4, 0, 0),
1157 F(266500000, P_BIMC, 4, 0, 0),
1158 F(400000000, P_GPLL0, 2, 0, 0),
1159 F(533000000, P_BIMC, 2, 0, 0),
1164 .cmd_rcgr = 0x31028,
1178 F(80000000, P_GPLL0, 10, 0, 0),
1183 .cmd_rcgr = 0x41010,
1196 F(3200000, P_XO, 6, 0, 0),
1197 F(6400000, P_XO, 3, 0, 0),
1198 F(9600000, P_XO, 2, 0, 0),
1199 F(19200000, P_XO, 1, 0, 0),
1201 F(66670000, P_GPLL0, 12, 0, 0),
1202 F(80000000, P_GPLL0, 10, 0, 0),
1203 F(100000000, P_GPLL0, 8, 0, 0),
1208 .cmd_rcgr = 0x1c010,
1222 .halt_reg = 0x1c028,
1224 .enable_reg = 0x1c028,
1225 .enable_mask = BIT(0),
1239 .halt_reg = 0x1c024,
1241 .enable_reg = 0x1c024,
1242 .enable_mask = BIT(0),
1268 F(1600000, P_XO, 12, 0, 0),
1272 F(2400000, P_XO, 8, 0, 0),
1276 F(4800000, P_XO, 4, 0, 0),
1280 F(9600000, P_XO, 2, 0, 0),
1287 .cmd_rcgr = 0x1c054,
1301 .halt_reg = 0x1c068,
1303 .enable_reg = 0x1c068,
1304 .enable_mask = BIT(0),
1318 .cmd_rcgr = 0x1c06c,
1332 .halt_reg = 0x1c080,
1334 .enable_reg = 0x1c080,
1335 .enable_mask = BIT(0),
1349 .cmd_rcgr = 0x1c084,
1363 .halt_reg = 0x1c098,
1365 .enable_reg = 0x1c098,
1366 .enable_mask = BIT(0),
1380 F(19200000, P_XO, 1, 0, 0),
1385 .cmd_rcgr = 0x1c034,
1398 .halt_reg = 0x1c04c,
1400 .enable_reg = 0x1c04c,
1401 .enable_mask = BIT(0),
1415 .halt_reg = 0x1c050,
1417 .enable_reg = 0x1c050,
1418 .enable_mask = BIT(0),
1432 F(9600000, P_XO, 2, 0, 0),
1434 F(19200000, P_XO, 1, 0, 0),
1435 F(11289600, P_EXT_MCLK, 1, 0, 0),
1440 .cmd_rcgr = 0x1c09c,
1454 .halt_reg = 0x1c0b0,
1456 .enable_reg = 0x1c0b0,
1457 .enable_mask = BIT(0),
1471 .halt_reg = 0x1c000,
1473 .enable_reg = 0x1c000,
1474 .enable_mask = BIT(0),
1487 .halt_reg = 0x1c004,
1489 .enable_reg = 0x1c004,
1490 .enable_mask = BIT(0),
1503 F(100000000, P_GPLL0, 8, 0, 0),
1504 F(160000000, P_GPLL0, 5, 0, 0),
1505 F(228570000, P_GPLL0, 3.5, 0, 0),
1510 .cmd_rcgr = 0x4C000,
1524 .halt_reg = 0x01008,
1527 .enable_reg = 0x45004,
1541 .halt_reg = 0x01004,
1543 .enable_reg = 0x01004,
1544 .enable_mask = BIT(0),
1558 .halt_reg = 0x02008,
1560 .enable_reg = 0x02008,
1561 .enable_mask = BIT(0),
1575 .halt_reg = 0x02004,
1577 .enable_reg = 0x02004,
1578 .enable_mask = BIT(0),
1592 .halt_reg = 0x03010,
1594 .enable_reg = 0x03010,
1595 .enable_mask = BIT(0),
1609 .halt_reg = 0x0300c,
1611 .enable_reg = 0x0300c,
1612 .enable_mask = BIT(0),
1626 .halt_reg = 0x04020,
1628 .enable_reg = 0x04020,
1629 .enable_mask = BIT(0),
1643 .halt_reg = 0x0401c,
1645 .enable_reg = 0x0401c,
1646 .enable_mask = BIT(0),
1660 .halt_reg = 0x05020,
1662 .enable_reg = 0x05020,
1663 .enable_mask = BIT(0),
1677 .halt_reg = 0x0501c,
1679 .enable_reg = 0x0501c,
1680 .enable_mask = BIT(0),
1694 .halt_reg = 0x06020,
1696 .enable_reg = 0x06020,
1697 .enable_mask = BIT(0),
1711 .halt_reg = 0x0601c,
1713 .enable_reg = 0x0601c,
1714 .enable_mask = BIT(0),
1728 .halt_reg = 0x07020,
1730 .enable_reg = 0x07020,
1731 .enable_mask = BIT(0),
1745 .halt_reg = 0x0701c,
1747 .enable_reg = 0x0701c,
1748 .enable_mask = BIT(0),
1762 .halt_reg = 0x0203c,
1764 .enable_reg = 0x0203c,
1765 .enable_mask = BIT(0),
1779 .halt_reg = 0x0302c,
1781 .enable_reg = 0x0302c,
1782 .enable_mask = BIT(0),
1796 .halt_reg = 0x1300c,
1799 .enable_reg = 0x45004,
1813 .halt_reg = 0x5101c,
1815 .enable_reg = 0x5101c,
1816 .enable_mask = BIT(0),
1830 .halt_reg = 0x51018,
1832 .enable_reg = 0x51018,
1833 .enable_mask = BIT(0),
1847 .halt_reg = 0x4e040,
1849 .enable_reg = 0x4e040,
1850 .enable_mask = BIT(0),
1864 .halt_reg = 0x4e03c,
1866 .enable_reg = 0x4e03c,
1867 .enable_mask = BIT(0),
1881 .halt_reg = 0x4e048,
1883 .enable_reg = 0x4e048,
1884 .enable_mask = BIT(0),
1898 .halt_reg = 0x4e058,
1900 .enable_reg = 0x4e058,
1901 .enable_mask = BIT(0),
1915 .halt_reg = 0x4e050,
1917 .enable_reg = 0x4e050,
1918 .enable_mask = BIT(0),
1932 .halt_reg = 0x4f040,
1934 .enable_reg = 0x4f040,
1935 .enable_mask = BIT(0),
1949 .halt_reg = 0x4f03c,
1951 .enable_reg = 0x4f03c,
1952 .enable_mask = BIT(0),
1966 .halt_reg = 0x4f048,
1968 .enable_reg = 0x4f048,
1969 .enable_mask = BIT(0),
1983 .halt_reg = 0x4f058,
1985 .enable_reg = 0x4f058,
1986 .enable_mask = BIT(0),
2000 .halt_reg = 0x4f050,
2002 .enable_reg = 0x4f050,
2003 .enable_mask = BIT(0),
2017 .halt_reg = 0x58050,
2019 .enable_reg = 0x58050,
2020 .enable_mask = BIT(0),
2034 .halt_reg = 0x54018,
2036 .enable_reg = 0x54018,
2037 .enable_mask = BIT(0),
2051 .halt_reg = 0x55018,
2053 .enable_reg = 0x55018,
2054 .enable_mask = BIT(0),
2068 .halt_reg = 0x50004,
2070 .enable_reg = 0x50004,
2071 .enable_mask = BIT(0),
2085 .halt_reg = 0x57020,
2087 .enable_reg = 0x57020,
2088 .enable_mask = BIT(0),
2102 .halt_reg = 0x57024,
2104 .enable_reg = 0x57024,
2105 .enable_mask = BIT(0),
2119 .halt_reg = 0x57028,
2121 .enable_reg = 0x57028,
2122 .enable_mask = BIT(0),
2136 .halt_reg = 0x52018,
2138 .enable_reg = 0x52018,
2139 .enable_mask = BIT(0),
2153 .halt_reg = 0x53018,
2155 .enable_reg = 0x53018,
2156 .enable_mask = BIT(0),
2170 .halt_reg = 0x5600c,
2172 .enable_reg = 0x5600c,
2173 .enable_mask = BIT(0),
2187 .halt_reg = 0x4e01c,
2189 .enable_reg = 0x4e01c,
2190 .enable_mask = BIT(0),
2204 .halt_reg = 0x4f01c,
2206 .enable_reg = 0x4f01c,
2207 .enable_mask = BIT(0),
2221 .halt_reg = 0x5a014,
2223 .enable_reg = 0x5a014,
2224 .enable_mask = BIT(0),
2238 .halt_reg = 0x56004,
2240 .enable_reg = 0x56004,
2241 .enable_mask = BIT(0),
2255 .halt_reg = 0x58040,
2257 .enable_reg = 0x58040,
2258 .enable_mask = BIT(0),
2272 .halt_reg = 0x5803c,
2274 .enable_reg = 0x5803c,
2275 .enable_mask = BIT(0),
2289 .halt_reg = 0x58038,
2291 .enable_reg = 0x58038,
2292 .enable_mask = BIT(0),
2306 .halt_reg = 0x58044,
2308 .enable_reg = 0x58044,
2309 .enable_mask = BIT(0),
2323 .halt_reg = 0x58048,
2325 .enable_reg = 0x58048,
2326 .enable_mask = BIT(0),
2340 .halt_reg = 0x16024,
2343 .enable_reg = 0x45004,
2344 .enable_mask = BIT(0),
2358 .halt_reg = 0x16020,
2361 .enable_reg = 0x45004,
2376 .halt_reg = 0x1601c,
2379 .enable_reg = 0x45004,
2394 .halt_reg = 0x59024,
2396 .enable_reg = 0x59024,
2397 .enable_mask = BIT(0),
2411 .halt_reg = 0x08000,
2413 .enable_reg = 0x08000,
2414 .enable_mask = BIT(0),
2428 .halt_reg = 0x09000,
2430 .enable_reg = 0x09000,
2431 .enable_mask = BIT(0),
2445 .halt_reg = 0x0a000,
2447 .enable_reg = 0x0a000,
2448 .enable_mask = BIT(0),
2462 .halt_reg = 0x4d07c,
2464 .enable_reg = 0x4d07c,
2465 .enable_mask = BIT(0),
2479 .halt_reg = 0x4d080,
2481 .enable_reg = 0x4d080,
2482 .enable_mask = BIT(0),
2496 .halt_reg = 0x4d094,
2498 .enable_reg = 0x4d094,
2499 .enable_mask = BIT(0),
2513 .halt_reg = 0x4d098,
2515 .enable_reg = 0x4d098,
2516 .enable_mask = BIT(0),
2530 .halt_reg = 0x4D088,
2532 .enable_reg = 0x4D088,
2533 .enable_mask = BIT(0),
2547 .halt_reg = 0x4d084,
2549 .enable_reg = 0x4d084,
2550 .enable_mask = BIT(0),
2564 .halt_reg = 0x4d090,
2566 .enable_reg = 0x4d090,
2567 .enable_mask = BIT(0),
2581 .halt_reg = 0x49000,
2583 .enable_reg = 0x49000,
2584 .enable_mask = BIT(0),
2598 .halt_reg = 0x49004,
2600 .enable_reg = 0x49004,
2601 .enable_mask = BIT(0),
2615 .halt_reg = 0x59028,
2617 .enable_reg = 0x59028,
2618 .enable_mask = BIT(0),
2632 .halt_reg = 0x59020,
2634 .enable_reg = 0x59020,
2635 .enable_mask = BIT(0),
2649 .halt_reg = 0x4400c,
2651 .enable_reg = 0x4400c,
2652 .enable_mask = BIT(0),
2666 .halt_reg = 0x44004,
2668 .enable_reg = 0x44004,
2669 .enable_mask = BIT(0),
2683 .halt_reg = 0x13004,
2686 .enable_reg = 0x45004,
2700 .halt_reg = 0x4201c,
2702 .enable_reg = 0x4201c,
2703 .enable_mask = BIT(0),
2717 .halt_reg = 0x42018,
2719 .enable_reg = 0x42018,
2720 .enable_mask = BIT(0),
2734 .halt_reg = 0x4301c,
2736 .enable_reg = 0x4301c,
2737 .enable_mask = BIT(0),
2751 .halt_reg = 0x43018,
2753 .enable_reg = 0x43018,
2754 .enable_mask = BIT(0),
2768 .cmd_rcgr = 0x32004,
2781 .halt_reg = 0x12018,
2783 .enable_reg = 0x4500c,
2797 .halt_reg = 0x12020,
2799 .enable_reg = 0x4500c,
2813 .halt_reg = 0x12044,
2815 .enable_reg = 0x4500c,
2830 .halt_reg = 0x31024,
2832 .enable_reg = 0x31024,
2833 .enable_mask = BIT(0),
2847 .halt_reg = 0x31040,
2849 .enable_reg = 0x31040,
2850 .enable_mask = BIT(0),
2864 .halt_reg = 0x12034,
2866 .enable_reg = 0x4500c,
2881 .halt_reg = 0x1201c,
2883 .enable_reg = 0x4500c,
2898 .halt_reg = 0x12038,
2900 .enable_reg = 0x4500c,
2915 .halt_reg = 0x12014,
2917 .enable_reg = 0x4500c,
2932 .halt_reg = 0x1203c,
2934 .enable_reg = 0x4500c,
2949 .halt_reg = 0x4102c,
2951 .enable_reg = 0x4102c,
2952 .enable_mask = BIT(0),
2966 .halt_reg = 0x41008,
2968 .enable_reg = 0x41008,
2969 .enable_mask = BIT(0),
2983 .halt_reg = 0x41004,
2985 .enable_reg = 0x41004,
2986 .enable_mask = BIT(0),
3000 .halt_reg = 0x4c020,
3002 .enable_reg = 0x4c020,
3003 .enable_mask = BIT(0),
3017 .halt_reg = 0x4c024,
3019 .enable_reg = 0x4c024,
3020 .enable_mask = BIT(0),
3034 .halt_reg = 0x4c01c,
3036 .enable_reg = 0x4c01c,
3037 .enable_mask = BIT(0),
3051 .gdscr = 0x4c018,
3059 .gdscr = 0x4d078,
3067 .gdscr = 0x5701c,
3075 .gdscr = 0x58034,
3083 .gdscr = 0x5901c,
3263 [GCC_BLSP1_BCR] = { 0x01000 },
3264 [GCC_BLSP1_QUP1_BCR] = { 0x02000 },
3265 [GCC_BLSP1_UART1_BCR] = { 0x02038 },
3266 [GCC_BLSP1_QUP2_BCR] = { 0x03008 },
3267 [GCC_BLSP1_UART2_BCR] = { 0x03028 },
3268 [GCC_BLSP1_QUP3_BCR] = { 0x04018 },
3269 [GCC_BLSP1_QUP4_BCR] = { 0x05018 },
3270 [GCC_BLSP1_QUP5_BCR] = { 0x06018 },
3271 [GCC_BLSP1_QUP6_BCR] = { 0x07018 },
3272 [GCC_IMEM_BCR] = { 0x0e000 },
3273 [GCC_SMMU_BCR] = { 0x12000 },
3274 [GCC_APSS_TCU_BCR] = { 0x12050 },
3275 [GCC_SMMU_XPU_BCR] = { 0x12054 },
3276 [GCC_PCNOC_TBU_BCR] = { 0x12058 },
3277 [GCC_PRNG_BCR] = { 0x13000 },
3278 [GCC_BOOT_ROM_BCR] = { 0x13008 },
3279 [GCC_CRYPTO_BCR] = { 0x16000 },
3280 [GCC_SEC_CTRL_BCR] = { 0x1a000 },
3281 [GCC_AUDIO_CORE_BCR] = { 0x1c008 },
3282 [GCC_ULT_AUDIO_BCR] = { 0x1c0b4 },
3283 [GCC_DEHR_BCR] = { 0x1f000 },
3284 [GCC_SYSTEM_NOC_BCR] = { 0x26000 },
3285 [GCC_PCNOC_BCR] = { 0x27018 },
3286 [GCC_TCSR_BCR] = { 0x28000 },
3287 [GCC_QDSS_BCR] = { 0x29000 },
3288 [GCC_DCD_BCR] = { 0x2a000 },
3289 [GCC_MSG_RAM_BCR] = { 0x2b000 },
3290 [GCC_MPM_BCR] = { 0x2c000 },
3291 [GCC_SPMI_BCR] = { 0x2e000 },
3292 [GCC_SPDM_BCR] = { 0x2f000 },
3293 [GCC_MM_SPDM_BCR] = { 0x2f024 },
3294 [GCC_BIMC_BCR] = { 0x31000 },
3295 [GCC_RBCPR_BCR] = { 0x33000 },
3296 [GCC_TLMM_BCR] = { 0x34000 },
3297 [GCC_USB_HS_BCR] = { 0x41000 },
3298 [GCC_USB2A_PHY_BCR] = { 0x41028 },
3299 [GCC_SDCC1_BCR] = { 0x42000 },
3300 [GCC_SDCC2_BCR] = { 0x43000 },
3301 [GCC_PDM_BCR] = { 0x44000 },
3302 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000 },
3303 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000 },
3304 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008 },
3305 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010 },
3306 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018 },
3307 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020 },
3308 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028 },
3309 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030 },
3310 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038 },
3311 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040 },
3312 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048 },
3313 [GCC_MMSS_BCR] = { 0x4b000 },
3314 [GCC_VENUS0_BCR] = { 0x4c014 },
3315 [GCC_MDSS_BCR] = { 0x4d074 },
3316 [GCC_CAMSS_PHY0_BCR] = { 0x4e018 },
3317 [GCC_CAMSS_CSI0_BCR] = { 0x4e038 },
3318 [GCC_CAMSS_CSI0PHY_BCR] = { 0x4e044 },
3319 [GCC_CAMSS_CSI0RDI_BCR] = { 0x4e04c },
3320 [GCC_CAMSS_CSI0PIX_BCR] = { 0x4e054 },
3321 [GCC_CAMSS_PHY1_BCR] = { 0x4f018 },
3322 [GCC_CAMSS_CSI1_BCR] = { 0x4f038 },
3323 [GCC_CAMSS_CSI1PHY_BCR] = { 0x4f044 },
3324 [GCC_CAMSS_CSI1RDI_BCR] = { 0x4f04c },
3325 [GCC_CAMSS_CSI1PIX_BCR] = { 0x4f054 },
3326 [GCC_CAMSS_ISPIF_BCR] = { 0x50000 },
3327 [GCC_CAMSS_CCI_BCR] = { 0x51014 },
3328 [GCC_CAMSS_MCLK0_BCR] = { 0x52014 },
3329 [GCC_CAMSS_MCLK1_BCR] = { 0x53014 },
3330 [GCC_CAMSS_GP0_BCR] = { 0x54014 },
3331 [GCC_CAMSS_GP1_BCR] = { 0x55014 },
3332 [GCC_CAMSS_TOP_BCR] = { 0x56000 },
3333 [GCC_CAMSS_MICRO_BCR] = { 0x56008 },
3334 [GCC_CAMSS_JPEG_BCR] = { 0x57018 },
3335 [GCC_CAMSS_VFE_BCR] = { 0x58030 },
3336 [GCC_CAMSS_CSI_VFE0_BCR] = { 0x5804c },
3337 [GCC_OXILI_BCR] = { 0x59018 },
3338 [GCC_GMEM_BCR] = { 0x5902c },
3339 [GCC_CAMSS_AHB_BCR] = { 0x5a018 },
3340 [GCC_MDP_TBU_BCR] = { 0x62000 },
3341 [GCC_GFX_TBU_BCR] = { 0x63000 },
3342 [GCC_GFX_TCU_BCR] = { 0x64000 },
3343 [GCC_MSS_TBU_AXI_BCR] = { 0x65000 },
3344 [GCC_MSS_TBU_GSS_AXI_BCR] = { 0x66000 },
3345 [GCC_MSS_TBU_Q6_AXI_BCR] = { 0x67000 },
3346 [GCC_GTCU_AHB_BCR] = { 0x68000 },
3347 [GCC_SMMU_CFG_BCR] = { 0x69000 },
3348 [GCC_VFE_TBU_BCR] = { 0x6a000 },
3349 [GCC_VENUS_TBU_BCR] = { 0x6b000 },
3350 [GCC_JPEG_TBU_BCR] = { 0x6c000 },
3351 [GCC_PRONTO_TBU_BCR] = { 0x6d000 },
3352 [GCC_SMMU_CATS_BCR] = { 0x7c000 },
3359 .max_register = 0x80000,