Lines Matching +full:0 +full:x2c000
58 { P_XO, 0 },
69 { P_XO, 0 },
81 { P_XO, 0 },
94 { P_XO, 0 },
107 { P_XO, 0 },
120 { P_XO, 0 },
131 { P_USB3PHY_0_PIPE, 0 },
141 { P_USB3PHY_1_PIPE, 0 },
151 { P_PCIE20_PHY0_PIPE, 0 },
161 { P_PCIE20_PHY1_PIPE, 0 },
173 { P_XO, 0 },
187 { P_XO, 0 },
201 { P_XO, 0 },
214 { P_XO, 0 },
229 { P_XO, 0 },
243 { P_XO, 0 },
257 { P_XO, 0 },
272 { P_XO, 0 },
286 { P_XO, 0 },
302 { P_XO, 0 },
321 { P_XO, 0 },
342 { P_XO, 0 },
360 { P_XO, 0 },
376 { P_XO, 0 },
392 { P_XO, 0 },
400 .offset = 0x21000,
403 .enable_reg = 0x0b000,
404 .enable_mask = BIT(0),
431 .offset = 0x21000,
445 .offset = 0x4a000,
448 .enable_reg = 0x0b000,
463 .offset = 0x4a000,
478 .offset = 0x24000,
481 .enable_reg = 0x0b000,
496 .offset = 0x24000,
511 .offset = 0x37000,
515 .enable_reg = 0x0b000,
530 .offset = 0x37000,
559 .offset = 0x25000,
563 .enable_reg = 0x0b000,
577 .offset = 0x25000,
592 .offset = 0x22000,
595 .enable_reg = 0x0b000,
609 .offset = 0x22000,
624 F(19200000, P_XO, 1, 0, 0),
625 F(50000000, P_GPLL0, 16, 0, 0),
626 F(100000000, P_GPLL0, 8, 0, 0),
631 .cmd_rcgr = 0x27000,
659 .halt_reg = 0x30000,
661 .enable_reg = 0x30000,
675 F(19200000, P_XO, 1, 0, 0),
676 F(25000000, P_GPLL0_DIV2, 16, 0, 0),
677 F(50000000, P_GPLL0, 16, 0, 0),
682 .cmd_rcgr = 0x0200c,
696 F(4800000, P_XO, 4, 0, 0),
697 F(9600000, P_XO, 2, 0, 0),
700 F(19200000, P_XO, 1, 0, 0),
702 F(50000000, P_GPLL0, 16, 0, 0),
707 .cmd_rcgr = 0x02024,
721 .cmd_rcgr = 0x03000,
734 .cmd_rcgr = 0x03014,
748 .cmd_rcgr = 0x04000,
761 .cmd_rcgr = 0x04014,
775 .cmd_rcgr = 0x05000,
788 .cmd_rcgr = 0x05014,
802 .cmd_rcgr = 0x06000,
815 .cmd_rcgr = 0x06014,
829 .cmd_rcgr = 0x07000,
842 .cmd_rcgr = 0x07014,
860 F(19200000, P_XO, 1, 0, 0),
876 .cmd_rcgr = 0x02044,
890 .cmd_rcgr = 0x03034,
904 .cmd_rcgr = 0x04034,
918 .cmd_rcgr = 0x05034,
932 .cmd_rcgr = 0x06034,
946 .cmd_rcgr = 0x07034,
960 F(19200000, P_XO, 1, 0, 0),
961 F(200000000, P_GPLL0, 4, 0, 0),
966 .cmd_rcgr = 0x75054,
979 F(19200000, P_XO, 1, 0, 0),
983 .cmd_rcgr = 0x75024,
997 .reg = 0x7501c,
1013 .cmd_rcgr = 0x76054,
1026 .cmd_rcgr = 0x76024,
1040 .reg = 0x7601c,
1060 F(96000000, P_GPLL2, 12, 0, 0),
1061 F(177777778, P_GPLL0, 4.5, 0, 0),
1062 F(192000000, P_GPLL2, 6, 0, 0),
1063 F(384000000, P_GPLL2, 3, 0, 0),
1068 .cmd_rcgr = 0x42004,
1082 F(19200000, P_XO, 1, 0, 0),
1083 F(160000000, P_GPLL0, 5, 0, 0),
1084 F(308570000, P_GPLL6, 3.5, 0, 0),
1088 .cmd_rcgr = 0x5d000,
1102 .cmd_rcgr = 0x43004,
1116 F(80000000, P_GPLL0_DIV2, 5, 0, 0),
1117 F(100000000, P_GPLL0, 8, 0, 0),
1118 F(133330000, P_GPLL0, 6, 0, 0),
1123 .cmd_rcgr = 0x3e00c,
1137 F(19200000, P_XO, 1, 0, 0),
1142 .cmd_rcgr = 0x3e05c,
1156 F(19200000, P_XO, 1, 0, 0),
1163 .cmd_rcgr = 0x3e020,
1177 .reg = 0x3e048,
1193 .cmd_rcgr = 0x3f00c,
1207 .cmd_rcgr = 0x3f05c,
1221 .cmd_rcgr = 0x3f020,
1235 .reg = 0x3f048,
1251 .halt_reg = 0x30018,
1253 .enable_reg = 0x30018,
1282 F(19200000, P_XO, 1, 0, 0),
1283 F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1284 F(100000000, P_GPLL0, 8, 0, 0),
1285 F(133333333, P_GPLL0, 6, 0, 0),
1286 F(160000000, P_GPLL0, 5, 0, 0),
1287 F(200000000, P_GPLL0, 4, 0, 0),
1288 F(266666667, P_GPLL0, 3, 0, 0),
1293 .cmd_rcgr = 0x26004,
1321 F(19200000, P_XO, 1, 0, 0),
1322 F(200000000, P_GPLL0, 4, 0, 0),
1327 .cmd_rcgr = 0x68098,
1340 F(19200000, P_XO, 1, 0, 0),
1341 F(461500000, P_BIAS_PLL_NSS_NOC, 1, 0, 0),
1346 .cmd_rcgr = 0x68088,
1373 F(19200000, P_XO, 1, 0, 0),
1374 F(600000000, P_NSS_CRYPTO_PLL, 1, 0, 0),
1379 .cmd_rcgr = 0x68144,
1393 F(19200000, P_XO, 1, 0, 0),
1394 F(187200000, P_UBI32_PLL, 8, 0, 0),
1395 F(748800000, P_UBI32_PLL, 2, 0, 0),
1396 F(1497600000, P_UBI32_PLL, 1, 0, 0),
1397 F(1689600000, P_UBI32_PLL, 1, 0, 0),
1402 .cmd_rcgr = 0x68104,
1416 .reg = 0x68118,
1417 .shift = 0,
1433 .cmd_rcgr = 0x68124,
1447 .reg = 0x68138,
1448 .shift = 0,
1464 F(19200000, P_XO, 1, 0, 0),
1465 F(25000000, P_GPLL0_DIV2, 16, 0, 0),
1470 .cmd_rcgr = 0x68090,
1483 F(19200000, P_XO, 1, 0, 0),
1484 F(400000000, P_GPLL0, 2, 0, 0),
1489 .cmd_rcgr = 0x68158,
1502 F(19200000, P_XO, 1, 0, 0),
1503 F(300000000, P_BIAS_PLL, 1, 0, 0),
1508 .cmd_rcgr = 0x68080,
1535 F(19200000, P_XO, 1, 0, 0),
1536 F(25000000, P_UNIPHY0_RX, 5, 0, 0),
1537 F(125000000, P_UNIPHY0_RX, 1, 0, 0),
1542 .cmd_rcgr = 0x68020,
1555 .reg = 0x68400,
1556 .shift = 0,
1572 F(19200000, P_XO, 1, 0, 0),
1573 F(25000000, P_UNIPHY0_TX, 5, 0, 0),
1574 F(125000000, P_UNIPHY0_TX, 1, 0, 0),
1579 .cmd_rcgr = 0x68028,
1592 .reg = 0x68404,
1593 .shift = 0,
1609 .cmd_rcgr = 0x68030,
1622 .reg = 0x68410,
1623 .shift = 0,
1639 .cmd_rcgr = 0x68038,
1652 .reg = 0x68414,
1653 .shift = 0,
1669 .cmd_rcgr = 0x68040,
1682 .reg = 0x68420,
1683 .shift = 0,
1699 .cmd_rcgr = 0x68048,
1712 .reg = 0x68424,
1713 .shift = 0,
1729 .cmd_rcgr = 0x68050,
1742 .reg = 0x68430,
1743 .shift = 0,
1759 .cmd_rcgr = 0x68058,
1772 .reg = 0x68434,
1773 .shift = 0,
1789 F(19200000, P_XO, 1, 0, 0),
1790 F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
1791 F(78125000, P_UNIPHY1_RX, 4, 0, 0),
1792 F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
1793 F(156250000, P_UNIPHY1_RX, 2, 0, 0),
1794 F(312500000, P_UNIPHY1_RX, 1, 0, 0),
1799 .cmd_rcgr = 0x68060,
1812 .reg = 0x68440,
1813 .shift = 0,
1829 F(19200000, P_XO, 1, 0, 0),
1830 F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
1831 F(78125000, P_UNIPHY1_TX, 4, 0, 0),
1832 F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
1833 F(156250000, P_UNIPHY1_TX, 2, 0, 0),
1834 F(312500000, P_UNIPHY1_TX, 1, 0, 0),
1839 .cmd_rcgr = 0x68068,
1852 .reg = 0x68444,
1853 .shift = 0,
1869 F(19200000, P_XO, 1, 0, 0),
1870 F(25000000, P_UNIPHY2_RX, 12.5, 0, 0),
1871 F(78125000, P_UNIPHY2_RX, 4, 0, 0),
1872 F(125000000, P_UNIPHY2_RX, 2.5, 0, 0),
1873 F(156250000, P_UNIPHY2_RX, 2, 0, 0),
1874 F(312500000, P_UNIPHY2_RX, 1, 0, 0),
1879 .cmd_rcgr = 0x68070,
1892 .reg = 0x68450,
1893 .shift = 0,
1909 F(19200000, P_XO, 1, 0, 0),
1910 F(25000000, P_UNIPHY2_TX, 12.5, 0, 0),
1911 F(78125000, P_UNIPHY2_TX, 4, 0, 0),
1912 F(125000000, P_UNIPHY2_TX, 2.5, 0, 0),
1913 F(156250000, P_UNIPHY2_TX, 2, 0, 0),
1914 F(312500000, P_UNIPHY2_TX, 1, 0, 0),
1919 .cmd_rcgr = 0x68078,
1932 .reg = 0x68454,
1933 .shift = 0,
1949 F(40000000, P_GPLL0_DIV2, 10, 0, 0),
1950 F(80000000, P_GPLL0, 10, 0, 0),
1951 F(100000000, P_GPLL0, 8, 0, 0),
1952 F(160000000, P_GPLL0, 5, 0, 0),
1957 .cmd_rcgr = 0x16004,
1970 F(19200000, P_XO, 1, 0, 0),
1975 .cmd_rcgr = 0x08004,
1989 .cmd_rcgr = 0x09004,
2003 .cmd_rcgr = 0x0a004,
2017 .halt_reg = 0x01008,
2019 .enable_reg = 0x01008,
2020 .enable_mask = BIT(0),
2034 .halt_reg = 0x02008,
2036 .enable_reg = 0x02008,
2037 .enable_mask = BIT(0),
2051 .halt_reg = 0x02004,
2053 .enable_reg = 0x02004,
2054 .enable_mask = BIT(0),
2068 .halt_reg = 0x03010,
2070 .enable_reg = 0x03010,
2071 .enable_mask = BIT(0),
2085 .halt_reg = 0x0300c,
2087 .enable_reg = 0x0300c,
2088 .enable_mask = BIT(0),
2102 .halt_reg = 0x04010,
2104 .enable_reg = 0x04010,
2105 .enable_mask = BIT(0),
2119 .halt_reg = 0x0400c,
2121 .enable_reg = 0x0400c,
2122 .enable_mask = BIT(0),
2136 .halt_reg = 0x05010,
2138 .enable_reg = 0x05010,
2139 .enable_mask = BIT(0),
2153 .halt_reg = 0x0500c,
2155 .enable_reg = 0x0500c,
2156 .enable_mask = BIT(0),
2170 .halt_reg = 0x06010,
2172 .enable_reg = 0x06010,
2173 .enable_mask = BIT(0),
2187 .halt_reg = 0x0600c,
2189 .enable_reg = 0x0600c,
2190 .enable_mask = BIT(0),
2204 .halt_reg = 0x07010,
2206 .enable_reg = 0x07010,
2207 .enable_mask = BIT(0),
2221 .halt_reg = 0x0700c,
2223 .enable_reg = 0x0700c,
2224 .enable_mask = BIT(0),
2238 .halt_reg = 0x0203c,
2240 .enable_reg = 0x0203c,
2241 .enable_mask = BIT(0),
2255 .halt_reg = 0x0302c,
2257 .enable_reg = 0x0302c,
2258 .enable_mask = BIT(0),
2272 .halt_reg = 0x0402c,
2274 .enable_reg = 0x0402c,
2275 .enable_mask = BIT(0),
2289 .halt_reg = 0x0502c,
2291 .enable_reg = 0x0502c,
2292 .enable_mask = BIT(0),
2306 .halt_reg = 0x0602c,
2308 .enable_reg = 0x0602c,
2309 .enable_mask = BIT(0),
2323 .halt_reg = 0x0702c,
2325 .enable_reg = 0x0702c,
2326 .enable_mask = BIT(0),
2340 .halt_reg = 0x13004,
2343 .enable_reg = 0x0b004,
2358 .halt_reg = 0x57024,
2360 .enable_reg = 0x57024,
2361 .enable_mask = BIT(0),
2375 .halt_reg = 0x57020,
2377 .enable_reg = 0x57020,
2378 .enable_mask = BIT(0),
2392 .halt_reg = 0x75010,
2394 .enable_reg = 0x75010,
2395 .enable_mask = BIT(0),
2409 .halt_reg = 0x75014,
2411 .enable_reg = 0x75014,
2412 .enable_mask = BIT(0),
2426 .halt_reg = 0x75008,
2428 .enable_reg = 0x75008,
2429 .enable_mask = BIT(0),
2443 .halt_reg = 0x7500c,
2445 .enable_reg = 0x7500c,
2446 .enable_mask = BIT(0),
2460 .halt_reg = 0x75018,
2463 .enable_reg = 0x75018,
2464 .enable_mask = BIT(0),
2478 .halt_reg = 0x26048,
2480 .enable_reg = 0x26048,
2481 .enable_mask = BIT(0),
2495 .halt_reg = 0x76010,
2497 .enable_reg = 0x76010,
2498 .enable_mask = BIT(0),
2512 .halt_reg = 0x76014,
2514 .enable_reg = 0x76014,
2515 .enable_mask = BIT(0),
2529 .halt_reg = 0x76008,
2531 .enable_reg = 0x76008,
2532 .enable_mask = BIT(0),
2546 .halt_reg = 0x7600c,
2548 .enable_reg = 0x7600c,
2549 .enable_mask = BIT(0),
2563 .halt_reg = 0x76018,
2566 .enable_reg = 0x76018,
2567 .enable_mask = BIT(0),
2581 .halt_reg = 0x2604c,
2583 .enable_reg = 0x2604c,
2584 .enable_mask = BIT(0),
2598 .halt_reg = 0x3e044,
2600 .enable_reg = 0x3e044,
2601 .enable_mask = BIT(0),
2615 .halt_reg = 0x26040,
2617 .enable_reg = 0x26040,
2618 .enable_mask = BIT(0),
2632 .halt_reg = 0x3e000,
2634 .enable_reg = 0x3e000,
2635 .enable_mask = BIT(0),
2649 .halt_reg = 0x3e008,
2651 .enable_reg = 0x3e008,
2652 .enable_mask = BIT(0),
2666 .halt_reg = 0x3e080,
2668 .enable_reg = 0x3e080,
2669 .enable_mask = BIT(0),
2683 .halt_reg = 0x3e040,
2686 .enable_reg = 0x3e040,
2687 .enable_mask = BIT(0),
2701 .halt_reg = 0x3e004,
2703 .enable_reg = 0x3e004,
2704 .enable_mask = BIT(0),
2718 .halt_reg = 0x3f044,
2720 .enable_reg = 0x3f044,
2721 .enable_mask = BIT(0),
2735 .halt_reg = 0x26044,
2737 .enable_reg = 0x26044,
2738 .enable_mask = BIT(0),
2752 .halt_reg = 0x3f000,
2754 .enable_reg = 0x3f000,
2755 .enable_mask = BIT(0),
2769 .halt_reg = 0x3f008,
2771 .enable_reg = 0x3f008,
2772 .enable_mask = BIT(0),
2786 .halt_reg = 0x3f080,
2788 .enable_reg = 0x3f080,
2789 .enable_mask = BIT(0),
2803 .halt_reg = 0x3f040,
2806 .enable_reg = 0x3f040,
2807 .enable_mask = BIT(0),
2821 .halt_reg = 0x3f004,
2823 .enable_reg = 0x3f004,
2824 .enable_mask = BIT(0),
2838 .halt_reg = 0x4201c,
2840 .enable_reg = 0x4201c,
2841 .enable_mask = BIT(0),
2855 .halt_reg = 0x42018,
2857 .enable_reg = 0x42018,
2858 .enable_mask = BIT(0),
2872 .halt_reg = 0x5d014,
2874 .enable_reg = 0x5d014,
2875 .enable_mask = BIT(0),
2889 .halt_reg = 0x4301c,
2891 .enable_reg = 0x4301c,
2892 .enable_mask = BIT(0),
2906 .halt_reg = 0x43018,
2908 .enable_reg = 0x43018,
2909 .enable_mask = BIT(0),
2923 .halt_reg = 0x1d03c,
2925 .enable_reg = 0x1d03c,
2926 .enable_mask = BIT(0),
2940 .halt_reg = 0x68174,
2942 .enable_reg = 0x68174,
2943 .enable_mask = BIT(0),
2957 .halt_reg = 0x68170,
2959 .enable_reg = 0x68170,
2960 .enable_mask = BIT(0),
2974 .halt_reg = 0x68160,
2976 .enable_reg = 0x68160,
2977 .enable_mask = BIT(0),
2991 .halt_reg = 0x68164,
2993 .enable_reg = 0x68164,
2994 .enable_mask = BIT(0),
3008 .halt_reg = 0x68318,
3010 .enable_reg = 0x68318,
3011 .enable_mask = BIT(0),
3025 .halt_reg = 0x6819c,
3027 .enable_reg = 0x6819c,
3028 .enable_mask = BIT(0),
3042 .halt_reg = 0x68198,
3044 .enable_reg = 0x68198,
3045 .enable_mask = BIT(0),
3059 .halt_reg = 0x68178,
3061 .enable_reg = 0x68178,
3062 .enable_mask = BIT(0),
3076 .halt_reg = 0x68168,
3078 .enable_reg = 0x68168,
3079 .enable_mask = BIT(0),
3093 .halt_reg = 0x6833c,
3095 .enable_reg = 0x6833c,
3096 .enable_mask = BIT(0),
3110 .halt_reg = 0x68194,
3112 .enable_reg = 0x68194,
3113 .enable_mask = BIT(0),
3127 .halt_reg = 0x68190,
3129 .enable_reg = 0x68190,
3130 .enable_mask = BIT(0),
3144 .halt_reg = 0x68338,
3146 .enable_reg = 0x68338,
3147 .enable_mask = BIT(0),
3161 .halt_reg = 0x6816c,
3163 .enable_reg = 0x6816c,
3164 .enable_mask = BIT(0),
3178 .halt_reg = 0x6830c,
3180 .enable_reg = 0x6830c,
3181 .enable_mask = BIT(0),
3195 .halt_reg = 0x68308,
3197 .enable_reg = 0x68308,
3198 .enable_mask = BIT(0),
3212 .halt_reg = 0x68314,
3214 .enable_reg = 0x68314,
3215 .enable_mask = BIT(0),
3229 .halt_reg = 0x68304,
3231 .enable_reg = 0x68304,
3232 .enable_mask = BIT(0),
3246 .halt_reg = 0x68300,
3248 .enable_reg = 0x68300,
3249 .enable_mask = BIT(0),
3263 .halt_reg = 0x68180,
3265 .enable_reg = 0x68180,
3266 .enable_mask = BIT(0),
3280 .halt_reg = 0x68188,
3282 .enable_reg = 0x68188,
3283 .enable_mask = BIT(0),
3297 .halt_reg = 0x68184,
3299 .enable_reg = 0x68184,
3300 .enable_mask = BIT(0),
3314 .halt_reg = 0x68270,
3316 .enable_reg = 0x68270,
3317 .enable_mask = BIT(0),
3331 .halt_reg = 0x68274,
3333 .enable_reg = 0x68274,
3334 .enable_mask = BIT(0),
3348 .halt_reg = 0x6820c,
3350 .enable_reg = 0x6820c,
3351 .enable_mask = BIT(0),
3365 .halt_reg = 0x68200,
3367 .enable_reg = 0x68200,
3368 .enable_mask = BIT(0),
3382 .halt_reg = 0x68204,
3384 .enable_reg = 0x68204,
3385 .enable_mask = BIT(0),
3399 .halt_reg = 0x68210,
3401 .enable_reg = 0x68210,
3402 .enable_mask = BIT(0),
3416 .halt_reg = 0x68208,
3418 .enable_reg = 0x68208,
3419 .enable_mask = BIT(0),
3433 .halt_reg = 0x6822c,
3435 .enable_reg = 0x6822c,
3436 .enable_mask = BIT(0),
3450 .halt_reg = 0x68220,
3452 .enable_reg = 0x68220,
3453 .enable_mask = BIT(0),
3467 .halt_reg = 0x68224,
3469 .enable_reg = 0x68224,
3470 .enable_mask = BIT(0),
3484 .halt_reg = 0x68230,
3486 .enable_reg = 0x68230,
3487 .enable_mask = BIT(0),
3501 .halt_reg = 0x68228,
3503 .enable_reg = 0x68228,
3504 .enable_mask = BIT(0),
3518 .halt_reg = 0x56308,
3520 .enable_reg = 0x56308,
3521 .enable_mask = BIT(0),
3535 .halt_reg = 0x5630c,
3537 .enable_reg = 0x5630c,
3538 .enable_mask = BIT(0),
3552 .halt_reg = 0x58004,
3554 .enable_reg = 0x58004,
3555 .enable_mask = BIT(0),
3569 .halt_reg = 0x56008,
3571 .enable_reg = 0x56008,
3572 .enable_mask = BIT(0),
3586 .halt_reg = 0x5600c,
3588 .enable_reg = 0x5600c,
3589 .enable_mask = BIT(0),
3603 .halt_reg = 0x56108,
3605 .enable_reg = 0x56108,
3606 .enable_mask = BIT(0),
3620 .halt_reg = 0x5610c,
3622 .enable_reg = 0x5610c,
3623 .enable_mask = BIT(0),
3637 .halt_reg = 0x56208,
3639 .enable_reg = 0x56208,
3640 .enable_mask = BIT(0),
3654 .halt_reg = 0x5620c,
3656 .enable_reg = 0x5620c,
3657 .enable_mask = BIT(0),
3671 .halt_reg = 0x68240,
3673 .enable_reg = 0x68240,
3674 .enable_mask = BIT(0),
3688 .halt_reg = 0x68244,
3690 .enable_reg = 0x68244,
3691 .enable_mask = BIT(0),
3705 .halt_reg = 0x68248,
3707 .enable_reg = 0x68248,
3708 .enable_mask = BIT(0),
3722 .halt_reg = 0x6824c,
3724 .enable_reg = 0x6824c,
3725 .enable_mask = BIT(0),
3739 .halt_reg = 0x68250,
3741 .enable_reg = 0x68250,
3742 .enable_mask = BIT(0),
3756 .halt_reg = 0x68254,
3758 .enable_reg = 0x68254,
3759 .enable_mask = BIT(0),
3773 .halt_reg = 0x68258,
3775 .enable_reg = 0x68258,
3776 .enable_mask = BIT(0),
3790 .halt_reg = 0x6825c,
3792 .enable_reg = 0x6825c,
3793 .enable_mask = BIT(0),
3807 .halt_reg = 0x68260,
3809 .enable_reg = 0x68260,
3810 .enable_mask = BIT(0),
3824 .halt_reg = 0x68264,
3826 .enable_reg = 0x68264,
3827 .enable_mask = BIT(0),
3841 .halt_reg = 0x68268,
3843 .enable_reg = 0x68268,
3844 .enable_mask = BIT(0),
3858 .halt_reg = 0x6826c,
3860 .enable_reg = 0x6826c,
3861 .enable_mask = BIT(0),
3875 .halt_reg = 0x68320,
3877 .enable_reg = 0x68320,
3878 .enable_mask = BIT(0),
3892 .halt_reg = 0x68324,
3894 .enable_reg = 0x68324,
3895 .enable_mask = BIT(0),
3909 .halt_reg = 0x68328,
3911 .enable_reg = 0x68328,
3912 .enable_mask = BIT(0),
3926 .halt_reg = 0x6832c,
3928 .enable_reg = 0x6832c,
3929 .enable_mask = BIT(0),
3943 .halt_reg = 0x68330,
3945 .enable_reg = 0x68330,
3946 .enable_mask = BIT(0),
3960 .halt_reg = 0x68334,
3962 .enable_reg = 0x68334,
3963 .enable_mask = BIT(0),
3977 .halt_reg = 0x56010,
3979 .enable_reg = 0x56010,
3980 .enable_mask = BIT(0),
3994 .halt_reg = 0x56014,
3996 .enable_reg = 0x56014,
3997 .enable_mask = BIT(0),
4011 .halt_reg = 0x56018,
4013 .enable_reg = 0x56018,
4014 .enable_mask = BIT(0),
4028 .halt_reg = 0x5601c,
4030 .enable_reg = 0x5601c,
4031 .enable_mask = BIT(0),
4045 .halt_reg = 0x56020,
4047 .enable_reg = 0x56020,
4048 .enable_mask = BIT(0),
4062 .halt_reg = 0x56024,
4064 .enable_reg = 0x56024,
4065 .enable_mask = BIT(0),
4079 .halt_reg = 0x56028,
4081 .enable_reg = 0x56028,
4082 .enable_mask = BIT(0),
4096 .halt_reg = 0x5602c,
4098 .enable_reg = 0x5602c,
4099 .enable_mask = BIT(0),
4113 .halt_reg = 0x56030,
4115 .enable_reg = 0x56030,
4116 .enable_mask = BIT(0),
4130 .halt_reg = 0x56034,
4132 .enable_reg = 0x56034,
4133 .enable_mask = BIT(0),
4147 .halt_reg = 0x56110,
4149 .enable_reg = 0x56110,
4150 .enable_mask = BIT(0),
4164 .halt_reg = 0x56114,
4166 .enable_reg = 0x56114,
4167 .enable_mask = BIT(0),
4181 .halt_reg = 0x56210,
4183 .enable_reg = 0x56210,
4184 .enable_mask = BIT(0),
4198 .halt_reg = 0x56214,
4200 .enable_reg = 0x56214,
4201 .enable_mask = BIT(0),
4215 .halt_reg = 0x16024,
4218 .enable_reg = 0x0b004,
4219 .enable_mask = BIT(0),
4233 .halt_reg = 0x16020,
4236 .enable_reg = 0x0b004,
4251 .halt_reg = 0x1601c,
4254 .enable_reg = 0x0b004,
4269 .halt_reg = 0x08000,
4271 .enable_reg = 0x08000,
4272 .enable_mask = BIT(0),
4286 .halt_reg = 0x09000,
4288 .enable_reg = 0x09000,
4289 .enable_mask = BIT(0),
4303 .halt_reg = 0x0a000,
4305 .enable_reg = 0x0a000,
4306 .enable_mask = BIT(0),
4320 F(19200000, P_XO, 1, 0, 0),
4321 F(100000000, P_GPLL0, 8, 0, 0),
4326 .cmd_rcgr = 0x75070,
4340 .halt_reg = 0x75070,
4343 .enable_reg = 0x75070,
4358 .halt_reg = 0x75048,
4361 .enable_reg = 0x75048,
4362 .enable_mask = BIT(0),
4616 [GCC_BLSP1_BCR] = { 0x01000, 0 },
4617 [GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
4618 [GCC_BLSP1_UART1_BCR] = { 0x02038, 0 },
4619 [GCC_BLSP1_QUP2_BCR] = { 0x03008, 0 },
4620 [GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
4621 [GCC_BLSP1_QUP3_BCR] = { 0x04008, 0 },
4622 [GCC_BLSP1_UART3_BCR] = { 0x04028, 0 },
4623 [GCC_BLSP1_QUP4_BCR] = { 0x05008, 0 },
4624 [GCC_BLSP1_UART4_BCR] = { 0x05028, 0 },
4625 [GCC_BLSP1_QUP5_BCR] = { 0x06008, 0 },
4626 [GCC_BLSP1_UART5_BCR] = { 0x06028, 0 },
4627 [GCC_BLSP1_QUP6_BCR] = { 0x07008, 0 },
4628 [GCC_BLSP1_UART6_BCR] = { 0x07028, 0 },
4629 [GCC_IMEM_BCR] = { 0x0e000, 0 },
4630 [GCC_SMMU_BCR] = { 0x12000, 0 },
4631 [GCC_APSS_TCU_BCR] = { 0x12050, 0 },
4632 [GCC_SMMU_XPU_BCR] = { 0x12054, 0 },
4633 [GCC_PCNOC_TBU_BCR] = { 0x12058, 0 },
4634 [GCC_SMMU_CFG_BCR] = { 0x1208c, 0 },
4635 [GCC_PRNG_BCR] = { 0x13000, 0 },
4636 [GCC_BOOT_ROM_BCR] = { 0x13008, 0 },
4637 [GCC_CRYPTO_BCR] = { 0x16000, 0 },
4638 [GCC_WCSS_BCR] = { 0x18000, 0 },
4639 [GCC_WCSS_Q6_BCR] = { 0x18100, 0 },
4640 [GCC_NSS_BCR] = { 0x19000, 0 },
4641 [GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
4642 [GCC_ADSS_BCR] = { 0x1c000, 0 },
4643 [GCC_DDRSS_BCR] = { 0x1e000, 0 },
4644 [GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 },
4645 [GCC_PCNOC_BCR] = { 0x27018, 0 },
4646 [GCC_TCSR_BCR] = { 0x28000, 0 },
4647 [GCC_QDSS_BCR] = { 0x29000, 0 },
4648 [GCC_DCD_BCR] = { 0x2a000, 0 },
4649 [GCC_MSG_RAM_BCR] = { 0x2b000, 0 },
4650 [GCC_MPM_BCR] = { 0x2c000, 0 },
4651 [GCC_SPMI_BCR] = { 0x2e000, 0 },
4652 [GCC_SPDM_BCR] = { 0x2f000, 0 },
4653 [GCC_RBCPR_BCR] = { 0x33000, 0 },
4654 [GCC_RBCPR_MX_BCR] = { 0x33014, 0 },
4655 [GCC_TLMM_BCR] = { 0x34000, 0 },
4656 [GCC_RBCPR_WCSS_BCR] = { 0x3a000, 0 },
4657 [GCC_USB0_PHY_BCR] = { 0x3e034, 0 },
4658 [GCC_USB3PHY_0_PHY_BCR] = { 0x3e03c, 0 },
4659 [GCC_USB0_BCR] = { 0x3e070, 0 },
4660 [GCC_USB1_PHY_BCR] = { 0x3f034, 0 },
4661 [GCC_USB3PHY_1_PHY_BCR] = { 0x3f03c, 0 },
4662 [GCC_USB1_BCR] = { 0x3f070, 0 },
4663 [GCC_QUSB2_0_PHY_BCR] = { 0x4103c, 0 },
4664 [GCC_QUSB2_1_PHY_BCR] = { 0x41040, 0 },
4665 [GCC_SDCC1_BCR] = { 0x42000, 0 },
4666 [GCC_SDCC2_BCR] = { 0x43000, 0 },
4667 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000, 0 },
4668 [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x47008, 0 },
4669 [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x47010, 0 },
4670 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000, 0 },
4671 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008, 0 },
4672 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010, 0 },
4673 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018, 0 },
4674 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020, 0 },
4675 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028, 0 },
4676 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030, 0 },
4677 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038, 0 },
4678 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040, 0 },
4679 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048, 0 },
4680 [GCC_UNIPHY0_BCR] = { 0x56000, 0 },
4681 [GCC_UNIPHY1_BCR] = { 0x56100, 0 },
4682 [GCC_UNIPHY2_BCR] = { 0x56200, 0 },
4683 [GCC_CMN_12GPLL_BCR] = { 0x56300, 0 },
4684 [GCC_QPIC_BCR] = { 0x57018, 0 },
4685 [GCC_MDIO_BCR] = { 0x58000, 0 },
4686 [GCC_PCIE1_TBU_BCR] = { 0x65000, 0 },
4687 [GCC_WCSS_CORE_TBU_BCR] = { 0x66000, 0 },
4688 [GCC_WCSS_Q6_TBU_BCR] = { 0x67000, 0 },
4689 [GCC_USB0_TBU_BCR] = { 0x6a000, 0 },
4690 [GCC_USB1_TBU_BCR] = { 0x6a004, 0 },
4691 [GCC_PCIE0_TBU_BCR] = { 0x6b000, 0 },
4692 [GCC_NSS_NOC_TBU_BCR] = { 0x6e000, 0 },
4693 [GCC_PCIE0_BCR] = { 0x75004, 0 },
4694 [GCC_PCIE0_PHY_BCR] = { 0x75038, 0 },
4695 [GCC_PCIE0PHY_PHY_BCR] = { 0x7503c, 0 },
4696 [GCC_PCIE0_LINK_DOWN_BCR] = { 0x75044, 0 },
4697 [GCC_PCIE1_BCR] = { 0x76004, 0 },
4698 [GCC_PCIE1_PHY_BCR] = { 0x76038, 0 },
4699 [GCC_PCIE1PHY_PHY_BCR] = { 0x7603c, 0 },
4700 [GCC_PCIE1_LINK_DOWN_BCR] = { 0x76044, 0 },
4701 [GCC_DCC_BCR] = { 0x77000, 0 },
4702 [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x78000, 0 },
4703 [GCC_APC1_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x79000, 0 },
4704 [GCC_SMMU_CATS_BCR] = { 0x7c000, 0 },
4705 [GCC_UBI0_AXI_ARES] = { 0x68010, 0 },
4706 [GCC_UBI0_AHB_ARES] = { 0x68010, 1 },
4707 [GCC_UBI0_NC_AXI_ARES] = { 0x68010, 2 },
4708 [GCC_UBI0_DBG_ARES] = { 0x68010, 3 },
4709 [GCC_UBI0_CORE_CLAMP_ENABLE] = { 0x68010, 4 },
4710 [GCC_UBI0_CLKRST_CLAMP_ENABLE] = { 0x68010, 5 },
4711 [GCC_UBI1_AXI_ARES] = { 0x68010, 8 },
4712 [GCC_UBI1_AHB_ARES] = { 0x68010, 9 },
4713 [GCC_UBI1_NC_AXI_ARES] = { 0x68010, 10 },
4714 [GCC_UBI1_DBG_ARES] = { 0x68010, 11 },
4715 [GCC_UBI1_CORE_CLAMP_ENABLE] = { 0x68010, 12 },
4716 [GCC_UBI1_CLKRST_CLAMP_ENABLE] = { 0x68010, 13 },
4717 [GCC_NSS_CFG_ARES] = { 0x68010, 16 },
4718 [GCC_NSS_IMEM_ARES] = { 0x68010, 17 },
4719 [GCC_NSS_NOC_ARES] = { 0x68010, 18 },
4720 [GCC_NSS_CRYPTO_ARES] = { 0x68010, 19 },
4721 [GCC_NSS_CSR_ARES] = { 0x68010, 20 },
4722 [GCC_NSS_CE_APB_ARES] = { 0x68010, 21 },
4723 [GCC_NSS_CE_AXI_ARES] = { 0x68010, 22 },
4724 [GCC_NSSNOC_CE_APB_ARES] = { 0x68010, 23 },
4725 [GCC_NSSNOC_CE_AXI_ARES] = { 0x68010, 24 },
4726 [GCC_NSSNOC_UBI0_AHB_ARES] = { 0x68010, 25 },
4727 [GCC_NSSNOC_UBI1_AHB_ARES] = { 0x68010, 26 },
4728 [GCC_NSSNOC_SNOC_ARES] = { 0x68010, 27 },
4729 [GCC_NSSNOC_CRYPTO_ARES] = { 0x68010, 28 },
4730 [GCC_NSSNOC_ATB_ARES] = { 0x68010, 29 },
4731 [GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x68010, 30 },
4732 [GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x68010, 31 },
4733 [GCC_PCIE0_PIPE_ARES] = { 0x75040, 0 },
4734 [GCC_PCIE0_SLEEP_ARES] = { 0x75040, 1 },
4735 [GCC_PCIE0_CORE_STICKY_ARES] = { 0x75040, 2 },
4736 [GCC_PCIE0_AXI_MASTER_ARES] = { 0x75040, 3 },
4737 [GCC_PCIE0_AXI_SLAVE_ARES] = { 0x75040, 4 },
4738 [GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },
4739 [GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },
4740 [GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 },
4741 [GCC_PCIE1_PIPE_ARES] = { 0x76040, 0 },
4742 [GCC_PCIE1_SLEEP_ARES] = { 0x76040, 1 },
4743 [GCC_PCIE1_CORE_STICKY_ARES] = { 0x76040, 2 },
4744 [GCC_PCIE1_AXI_MASTER_ARES] = { 0x76040, 3 },
4745 [GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 },
4746 [GCC_PCIE1_AHB_ARES] = { 0x76040, 5 },
4747 [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
4760 .max_register = 0x7fffc,