1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk-provider.h>
17 #define PLL_STATUS_LOCK			BIT(0)
28 #define PLL_INT_CTRL1_PD		BIT(24)
29 #define PLL_INT_CTRL1_DSMPD		BIT(25)
30 #define PLL_INT_CTRL1_FOUTPOSTDIVPD	BIT(26)
31 #define PLL_INT_CTRL1_FOUTVCOPD		BIT(27)
40 #define PLL_INT_CTRL2_BYPASS		BIT(28)
43 #define PLL_FRAC_CTRL3_PD		BIT(0)
44 #define PLL_FRAC_CTRL3_DACPD		BIT(1)
45 #define PLL_FRAC_CTRL3_DSMPD		BIT(2)
46 #define PLL_FRAC_CTRL3_FOUTPOSTDIVPD	BIT(3)
47 #define PLL_FRAC_CTRL3_FOUT4PHASEPD	BIT(4)
48 #define PLL_FRAC_CTRL3_FOUTVCOPD	BIT(5)
51 #define PLL_FRAC_CTRL4_BYPASS		BIT(28)
80 	return readl(pll->base + reg);  in pll_readl()
85 	writel(val, pll->base + reg);  in pll_writel()
134 	for (i = 0; i < pll->nr_rates; i++) {  in pll_get_params()
135 		if (pll->rates[i].fref == fref && pll->rates[i].fout == fout)  in pll_get_params()
136 			return &pll->rates[i];  in pll_get_params()
142 static long pll_round_rate(struct clk_hw *hw, unsigned long rate,  in pll_round_rate()  argument
148 	for (i = 0; i < pll->nr_rates; i++) {  in pll_round_rate()
149 		if (i > 0 && pll->rates[i].fref == *parent_rate &&  in pll_round_rate()
150 		    pll->rates[i].fout <= rate)  in pll_round_rate()
151 			return pll->rates[i - 1].fout;  in pll_round_rate()
154 	return pll->rates[0].fout;  in pll_round_rate()
193 static int pll_gf40lp_frac_set_rate(struct clk_hw *hw, unsigned long rate,  in pll_gf40lp_frac_set_rate()  argument
202 	if (rate < MIN_OUTPUT_FRAC || rate > MAX_OUTPUT_FRAC)  in pll_gf40lp_frac_set_rate()
203 		return -EINVAL;  in pll_gf40lp_frac_set_rate()
205 	params = pll_get_params(pll, parent_rate, rate);  in pll_gf40lp_frac_set_rate()
206 	if (!params || !params->refdiv)  in pll_gf40lp_frac_set_rate()
207 		return -EINVAL;  in pll_gf40lp_frac_set_rate()
210 	vco = params->fref;  in pll_gf40lp_frac_set_rate()
211 	vco *= (params->fbdiv << 24) + params->frac;  in pll_gf40lp_frac_set_rate()
212 	vco = div64_u64(vco, params->refdiv << 24);  in pll_gf40lp_frac_set_rate()
218 	val = div64_u64(params->fref, params->refdiv);  in pll_gf40lp_frac_set_rate()
223 		pr_warn("%s: PFD %llu is too high (max %llu)\n",  in pll_gf40lp_frac_set_rate()
229 	val |= (params->refdiv << PLL_CTRL1_REFDIV_SHIFT) |  in pll_gf40lp_frac_set_rate()
230 		(params->fbdiv << PLL_CTRL1_FBDIV_SHIFT);  in pll_gf40lp_frac_set_rate()
240 	    (params->postdiv1 != old_postdiv1 ||  in pll_gf40lp_frac_set_rate()
241 	     params->postdiv2 != old_postdiv2))  in pll_gf40lp_frac_set_rate()
244 	if (params->postdiv2 > params->postdiv1)  in pll_gf40lp_frac_set_rate()
252 	val |= (params->frac << PLL_FRAC_CTRL2_FRAC_SHIFT) |  in pll_gf40lp_frac_set_rate()
253 		(params->postdiv1 << PLL_FRAC_CTRL2_POSTDIV1_SHIFT) |  in pll_gf40lp_frac_set_rate()
254 		(params->postdiv2 << PLL_FRAC_CTRL2_POSTDIV2_SHIFT);  in pll_gf40lp_frac_set_rate()
258 	if (params->frac)  in pll_gf40lp_frac_set_rate()
273 	u64 val, prediv, fbdiv, frac, postdiv1, postdiv2, rate;  in pll_gf40lp_frac_recalc_rate()  local
286 	/* get operating mode (int/frac) and calculate rate accordingly */  in pll_gf40lp_frac_recalc_rate()
287 	rate = parent_rate;  in pll_gf40lp_frac_recalc_rate()
289 		rate *= (fbdiv << 24) + frac;  in pll_gf40lp_frac_recalc_rate()
291 		rate *= (fbdiv << 24);  in pll_gf40lp_frac_recalc_rate()
293 	rate = do_div_round_closest(rate, (prediv * postdiv1 * postdiv2) << 24);  in pll_gf40lp_frac_recalc_rate()
295 	return rate;  in pll_gf40lp_frac_recalc_rate()
350 static int pll_gf40lp_laint_set_rate(struct clk_hw *hw, unsigned long rate,  in pll_gf40lp_laint_set_rate()  argument
359 	if (rate < MIN_OUTPUT_LA || rate > MAX_OUTPUT_LA)  in pll_gf40lp_laint_set_rate()
360 		return -EINVAL;  in pll_gf40lp_laint_set_rate()
362 	params = pll_get_params(pll, parent_rate, rate);  in pll_gf40lp_laint_set_rate()
363 	if (!params || !params->refdiv)  in pll_gf40lp_laint_set_rate()
364 		return -EINVAL;  in pll_gf40lp_laint_set_rate()
366 	vco = div_u64(params->fref * params->fbdiv, params->refdiv);  in pll_gf40lp_laint_set_rate()
371 	val = div_u64(params->fref, params->refdiv);  in pll_gf40lp_laint_set_rate()
376 		pr_warn("%s: PFD %u is too high (max %u)\n",  in pll_gf40lp_laint_set_rate()
386 	    (params->postdiv1 != old_postdiv1 ||  in pll_gf40lp_laint_set_rate()
387 	     params->postdiv2 != old_postdiv2))  in pll_gf40lp_laint_set_rate()
390 	if (params->postdiv2 > params->postdiv1)  in pll_gf40lp_laint_set_rate()
397 	val |= (params->refdiv << PLL_CTRL1_REFDIV_SHIFT) |  in pll_gf40lp_laint_set_rate()
398 		(params->fbdiv << PLL_CTRL1_FBDIV_SHIFT) |  in pll_gf40lp_laint_set_rate()
399 		(params->postdiv1 << PLL_INT_CTRL1_POSTDIV1_SHIFT) |  in pll_gf40lp_laint_set_rate()
400 		(params->postdiv2 << PLL_INT_CTRL1_POSTDIV2_SHIFT);  in pll_gf40lp_laint_set_rate()
414 	u64 rate = parent_rate;  in pll_gf40lp_laint_recalc_rate()  local
424 	rate *= fbdiv;  in pll_gf40lp_laint_recalc_rate()
425 	rate = do_div_round_closest(rate, prediv * postdiv1 * postdiv2);  in pll_gf40lp_laint_recalc_rate()
427 	return rate;  in pll_gf40lp_laint_recalc_rate()
458 		return ERR_PTR(-ENOMEM);  in pll_register()
481 		return ERR_PTR(-EINVAL);  in pll_register()
484 	pll->hw.init = &init;  in pll_register()
485 	pll->base = base;  in pll_register()
486 	pll->rates = rates;  in pll_register()
487 	pll->nr_rates = nr_rates;  in pll_register()
489 	clk = clk_register(NULL, &pll->hw);  in pll_register()
505 				   0, p->base + pll[i].reg_base,  in pistachio_clk_register_pll()
508 		p->clk_data.clks[pll[i].id] = clk;  in pistachio_clk_register_pll()