Lines Matching +full:1 +full:mhz
25 * 0 = 400 MHz 400 MHz 800 MHz
26 * 2 = 667 MHz 667 MHz 2000 MHz
27 * 3 = 800 MHz 800 MHz 1600 MHz
34 * 1 = 667 MHz 667 MHz 2000 MHz
35 * 2 = 400 MHz 400 MHz 400 MHz
36 * 3 = 800 MHz 800 MHz 800 MHz
37 * 5 = 800 MHz 400 MHz 800 MHz
46 /* Tclk = 200MHz, no SaR dependency */ in mv98dx3236_get_tclk_freq()
98 {0, 1}, {3, 1}, {1, 1}, {1, 1},
99 {0, 1}, {1, 1}, {0, 1}, {0, 1},
103 {0, 1}, {1, 1}, {1, 1}, {1, 1},
104 {0, 1}, {1, 2}, {0, 1}, {0, 1},
108 {2, 1}, {0, 1}, {3, 1}, {2, 1},
109 {0, 1}, {0, 1}, {0, 1}, {0, 1},
113 {1, 1}, {0, 1}, {1, 1}, {1, 1},
114 {0, 1}, {0, 1}, {0, 1}, {0, 1},
127 *div = mv98dx4251_cpu_ddr_ratios[opt][1]; in mv98dx3236_get_clk_ratio()
130 *div = mv98dx3236_cpu_ddr_ratios[opt][1]; in mv98dx3236_get_clk_ratio()
136 *div = mv98dx4251_cpu_mpll_ratios[opt][1]; in mv98dx3236_get_clk_ratio()
139 *div = mv98dx3236_cpu_mpll_ratios[opt][1]; in mv98dx3236_get_clk_ratio()