2  * mmp2 clock framework source file
22 #include <dt-bindings/clock/marvell,mmp2.h>
23 #include <dt-bindings/power/marvell,mmp2.h>
183 	struct mmp_clk_unit *unit = &pxa_unit->unit;  in mmp2_main_clk_init()
188 	if (pxa_unit->model == CLK_MODEL_MMP3) {  in mmp2_main_clk_init()
190 					pxa_unit->mpmu_base,  in mmp2_main_clk_init()
194 					pxa_unit->mpmu_base,  in mmp2_main_clk_init()
203 				pxa_unit->mpmu_base + MPMU_UART_PLL,  in mmp2_main_clk_init()
210 				pxa_unit->mpmu_base + MPMU_I2S0_PLL,  in mmp2_main_clk_init()
215 				pxa_unit->mpmu_base + MPMU_I2S1_PLL,  in mmp2_main_clk_init()
219 	mmp_register_gate_clks(unit, mpmu_gate_clks, pxa_unit->mpmu_base,  in mmp2_main_clk_init()
286 	struct mmp_clk_unit *unit = &pxa_unit->unit;  in mmp2_apb_periph_clk_init()
288 	mmp_register_mux_clks(unit, apbc_mux_clks, pxa_unit->apbc_base,  in mmp2_apb_periph_clk_init()
291 	mmp_register_gate_clks(unit, apbc_gate_clks, pxa_unit->apbc_base,  in mmp2_apb_periph_clk_init()
294 	if (pxa_unit->model == CLK_MODEL_MMP3) {  in mmp2_apb_periph_clk_init()
295 		mmp_register_gate_clks(unit, mmp3_apbc_gate_clks, pxa_unit->apbc_base,  in mmp2_apb_periph_clk_init()
399 	struct mmp_clk_unit *unit = &pxa_unit->unit;  in mmp2_axi_periph_clk_init()
401 	sdh_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_SDH0;  in mmp2_axi_periph_clk_init()
407 	ccic0_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_CCIC0;  in mmp2_axi_periph_clk_init()
414 	ccic1_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_CCIC1;  in mmp2_axi_periph_clk_init()
421 	mmp_register_mux_clks(unit, apmu_mux_clks, pxa_unit->apmu_base,  in mmp2_axi_periph_clk_init()
424 	mmp_register_div_clks(unit, apmu_div_clks, pxa_unit->apmu_base,  in mmp2_axi_periph_clk_init()
427 	mmp_register_gate_clks(unit, apmu_gate_clks, pxa_unit->apmu_base,  in mmp2_axi_periph_clk_init()
430 	if (pxa_unit->model == CLK_MODEL_MMP3) {  in mmp2_axi_periph_clk_init()
431 		mmp_register_mux_clks(unit, mmp3_apmu_mux_clks, pxa_unit->apmu_base,  in mmp2_axi_periph_clk_init()
434 		mmp_register_div_clks(unit, mmp3_apmu_div_clks, pxa_unit->apmu_base,  in mmp2_axi_periph_clk_init()
437 		mmp_register_gate_clks(unit, mmp3_apmu_gate_clks, pxa_unit->apmu_base,  in mmp2_axi_periph_clk_init()
443 					pxa_unit->apmu_base + APMU_GPU,  in mmp2_axi_periph_clk_init()
450 					pxa_unit->apmu_base + APMU_GPU,  in mmp2_axi_periph_clk_init()
454 		mmp_register_gate_clks(unit, mmp2_apmu_gate_clks, pxa_unit->apmu_base,  in mmp2_axi_periph_clk_init()
472 		cells[i].reg = pxa_unit->apbc_base + apbc_gate_clks[i].offset;  in mmp2_clk_reset_init()
484 	if (pxa_unit->model == CLK_MODEL_MMP3) {  in mmp2_pm_domain_init()
485 		pxa_unit->pm_domains[MMP2_POWER_DOMAIN_GPU]  in mmp2_pm_domain_init()
487 				pxa_unit->apmu_base + APMU_GPU,  in mmp2_pm_domain_init()
490 		pxa_unit->pm_domains[MMP2_POWER_DOMAIN_GPU]  in mmp2_pm_domain_init()
492 				pxa_unit->apmu_base + APMU_GPU,  in mmp2_pm_domain_init()
496 	pxa_unit->pd_data.num_domains++;  in mmp2_pm_domain_init()
498 	pxa_unit->pm_domains[MMP2_POWER_DOMAIN_AUDIO]  in mmp2_pm_domain_init()
499 		= mmp_pm_domain_register("audio",  in mmp2_pm_domain_init()
500 			pxa_unit->apmu_base + APMU_AUDIO,  in mmp2_pm_domain_init()
502 	pxa_unit->pd_data.num_domains++;  in mmp2_pm_domain_init()
504 	if (pxa_unit->model == CLK_MODEL_MMP3) {  in mmp2_pm_domain_init()
505 		pxa_unit->pm_domains[MMP3_POWER_DOMAIN_CAMERA]  in mmp2_pm_domain_init()
507 				pxa_unit->apmu_base + APMU_CAMERA,  in mmp2_pm_domain_init()
509 		pxa_unit->pd_data.num_domains++;  in mmp2_pm_domain_init()
512 	pxa_unit->pd_data.domains = pxa_unit->pm_domains;  in mmp2_pm_domain_init()
513 	of_genpd_add_provider_onecell(np, &pxa_unit->pd_data);  in mmp2_pm_domain_init()
524 	if (of_device_is_compatible(np, "marvell,mmp3-clock"))  in mmp2_clk_init()
525 		pxa_unit->model = CLK_MODEL_MMP3;  in mmp2_clk_init()
527 		pxa_unit->model = CLK_MODEL_MMP2;  in mmp2_clk_init()
529 	pxa_unit->mpmu_base = of_iomap(np, 0);  in mmp2_clk_init()
530 	if (!pxa_unit->mpmu_base) {  in mmp2_clk_init()
535 	pxa_unit->apmu_base = of_iomap(np, 1);  in mmp2_clk_init()
536 	if (!pxa_unit->apmu_base) {  in mmp2_clk_init()
541 	pxa_unit->apbc_base = of_iomap(np, 2);  in mmp2_clk_init()
542 	if (!pxa_unit->apbc_base) {  in mmp2_clk_init()
549 	mmp_clk_init(np, &pxa_unit->unit, MMP2_NR_CLKS);  in mmp2_clk_init()
562 	iounmap(pxa_unit->apmu_base);  in mmp2_clk_init()
564 	iounmap(pxa_unit->mpmu_base);  in mmp2_clk_init()
569 CLK_OF_DECLARE(mmp2_clk, "marvell,mmp2-clock", mmp2_clk_init);
570 CLK_OF_DECLARE(mmp3_clk, "marvell,mmp3-clock", mmp2_clk_init);