Lines Matching +full:mmp +full:- +full:sspa
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * MMP Audio Clock Controller driver
8 #include <linux/clk-provider.h>
15 #include <dt-bindings/clock/marvell,mmp2-audio.h>
22 /* SSPA Audio Control Register */
33 /* SSPA Audio PLL Control 0 Register */
50 /* SSPA Audio PLL Control 1 Register */
123 aud_pll_ctrl0 = readl(priv->mmio_base + SSPA_AUD_PLL_CTRL0); in audio_pll_recalc_rate()
131 aud_pll_ctrl1 = readl(priv->mmio_base + SSPA_AUD_PLL_CTRL1); in audio_pll_recalc_rate()
214 writel(val, priv->mmio_base + SSPA_AUD_PLL_CTRL0); in audio_pll_set_rate()
218 writel(val, priv->mmio_base + SSPA_AUD_PLL_CTRL1); in audio_pll_set_rate()
224 return -ERANGE; in audio_pll_set_rate()
236 { .hw = &priv->audio_pll_hw }, in register_clocks()
240 { .hw = &priv->audio_pll_hw }, in register_clocks()
245 priv->audio_pll_hw.init = CLK_HW_INIT_FW_NAME("audio_pll", in register_clocks()
248 ret = devm_clk_hw_register(dev, &priv->audio_pll_hw); in register_clocks()
252 priv->sspa_mux.hw.init = CLK_HW_INIT_PARENTS_DATA("sspa_mux", in register_clocks()
255 priv->sspa_mux.reg = priv->mmio_base + SSPA_AUD_CTRL; in register_clocks()
256 priv->sspa_mux.mask = 1; in register_clocks()
257 priv->sspa_mux.shift = SSPA_AUD_CTRL_SSPA0_MUX_SHIFT; in register_clocks()
258 ret = devm_clk_hw_register(dev, &priv->sspa_mux.hw); in register_clocks()
262 priv->sysclk_div.hw.init = CLK_HW_INIT_HW("sys_div", in register_clocks()
263 &priv->sspa_mux.hw, &clk_divider_ops, in register_clocks()
265 priv->sysclk_div.reg = priv->mmio_base + SSPA_AUD_CTRL; in register_clocks()
266 priv->sysclk_div.shift = SSPA_AUD_CTRL_SYSCLK_DIV_SHIFT; in register_clocks()
267 priv->sysclk_div.width = 6; in register_clocks()
268 priv->sysclk_div.flags = CLK_DIVIDER_ONE_BASED; in register_clocks()
269 priv->sysclk_div.flags |= CLK_DIVIDER_ROUND_CLOSEST; in register_clocks()
270 priv->sysclk_div.flags |= CLK_DIVIDER_ALLOW_ZERO; in register_clocks()
271 ret = devm_clk_hw_register(dev, &priv->sysclk_div.hw); in register_clocks()
275 priv->sysclk_gate.hw.init = CLK_HW_INIT_HW("sys_clk", in register_clocks()
276 &priv->sysclk_div.hw, &clk_gate_ops, in register_clocks()
278 priv->sysclk_gate.reg = priv->mmio_base + SSPA_AUD_CTRL; in register_clocks()
279 priv->sysclk_gate.bit_idx = SSPA_AUD_CTRL_SYSCLK_SHIFT; in register_clocks()
280 ret = devm_clk_hw_register(dev, &priv->sysclk_gate.hw); in register_clocks()
284 priv->sspa0_div.hw.init = CLK_HW_INIT_HW("sspa0_div", in register_clocks()
285 &priv->sspa_mux.hw, &clk_divider_ops, 0); in register_clocks()
286 priv->sspa0_div.reg = priv->mmio_base + SSPA_AUD_CTRL; in register_clocks()
287 priv->sspa0_div.shift = SSPA_AUD_CTRL_SSPA0_DIV_SHIFT; in register_clocks()
288 priv->sspa0_div.width = 6; in register_clocks()
289 priv->sspa0_div.flags = CLK_DIVIDER_ONE_BASED; in register_clocks()
290 priv->sspa0_div.flags |= CLK_DIVIDER_ROUND_CLOSEST; in register_clocks()
291 priv->sspa0_div.flags |= CLK_DIVIDER_ALLOW_ZERO; in register_clocks()
292 ret = devm_clk_hw_register(dev, &priv->sspa0_div.hw); in register_clocks()
296 priv->sspa0_gate.hw.init = CLK_HW_INIT_HW("sspa0_clk", in register_clocks()
297 &priv->sspa0_div.hw, &clk_gate_ops, in register_clocks()
299 priv->sspa0_gate.reg = priv->mmio_base + SSPA_AUD_CTRL; in register_clocks()
300 priv->sspa0_gate.bit_idx = SSPA_AUD_CTRL_SSPA0_SHIFT; in register_clocks()
301 ret = devm_clk_hw_register(dev, &priv->sspa0_gate.hw); in register_clocks()
305 priv->sspa1_mux.hw.init = CLK_HW_INIT_PARENTS_DATA("sspa1_mux", in register_clocks()
308 priv->sspa1_mux.reg = priv->mmio_base + SSPA_AUD_CTRL; in register_clocks()
309 priv->sspa1_mux.mask = 1; in register_clocks()
310 priv->sspa1_mux.shift = SSPA_AUD_CTRL_SSPA1_MUX_SHIFT; in register_clocks()
311 ret = devm_clk_hw_register(dev, &priv->sspa1_mux.hw); in register_clocks()
315 priv->sspa1_div.hw.init = CLK_HW_INIT_HW("sspa1_div", in register_clocks()
316 &priv->sspa1_mux.hw, &clk_divider_ops, 0); in register_clocks()
317 priv->sspa1_div.reg = priv->mmio_base + SSPA_AUD_CTRL; in register_clocks()
318 priv->sspa1_div.shift = SSPA_AUD_CTRL_SSPA1_DIV_SHIFT; in register_clocks()
319 priv->sspa1_div.width = 6; in register_clocks()
320 priv->sspa1_div.flags = CLK_DIVIDER_ONE_BASED; in register_clocks()
321 priv->sspa1_div.flags |= CLK_DIVIDER_ROUND_CLOSEST; in register_clocks()
322 priv->sspa1_div.flags |= CLK_DIVIDER_ALLOW_ZERO; in register_clocks()
323 ret = devm_clk_hw_register(dev, &priv->sspa1_div.hw); in register_clocks()
327 priv->sspa1_gate.hw.init = CLK_HW_INIT_HW("sspa1_clk", in register_clocks()
328 &priv->sspa1_div.hw, &clk_gate_ops, in register_clocks()
330 priv->sspa1_gate.reg = priv->mmio_base + SSPA_AUD_CTRL; in register_clocks()
331 priv->sspa1_gate.bit_idx = SSPA_AUD_CTRL_SSPA1_SHIFT; in register_clocks()
332 ret = devm_clk_hw_register(dev, &priv->sspa1_gate.hw); in register_clocks()
336 priv->clk_data.hws[MMP2_CLK_AUDIO_SYSCLK] = &priv->sysclk_gate.hw; in register_clocks()
337 priv->clk_data.hws[MMP2_CLK_AUDIO_SSPA0] = &priv->sspa0_gate.hw; in register_clocks()
338 priv->clk_data.hws[MMP2_CLK_AUDIO_SSPA1] = &priv->sspa1_gate.hw; in register_clocks()
339 priv->clk_data.num = MMP2_CLK_AUDIO_NR_CLKS; in register_clocks()
341 return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, in register_clocks()
342 &priv->clk_data); in register_clocks()
350 priv = devm_kzalloc(&pdev->dev, in mmp2_audio_clk_probe()
355 return -ENOMEM; in mmp2_audio_clk_probe()
357 spin_lock_init(&priv->lock); in mmp2_audio_clk_probe()
360 priv->mmio_base = devm_platform_ioremap_resource(pdev, 0); in mmp2_audio_clk_probe()
361 if (IS_ERR(priv->mmio_base)) in mmp2_audio_clk_probe()
362 return PTR_ERR(priv->mmio_base); in mmp2_audio_clk_probe()
364 pm_runtime_enable(&pdev->dev); in mmp2_audio_clk_probe()
365 ret = pm_clk_create(&pdev->dev); in mmp2_audio_clk_probe()
369 ret = pm_clk_add(&pdev->dev, "audio"); in mmp2_audio_clk_probe()
373 ret = register_clocks(priv, &pdev->dev); in mmp2_audio_clk_probe()
380 pm_clk_destroy(&pdev->dev); in mmp2_audio_clk_probe()
382 pm_runtime_disable(&pdev->dev); in mmp2_audio_clk_probe()
389 pm_clk_destroy(&pdev->dev); in mmp2_audio_clk_remove()
390 pm_runtime_disable(&pdev->dev); in mmp2_audio_clk_remove()
399 priv->aud_ctrl = readl(priv->mmio_base + SSPA_AUD_CTRL); in mmp2_audio_clk_suspend()
400 priv->aud_pll_ctrl0 = readl(priv->mmio_base + SSPA_AUD_PLL_CTRL0); in mmp2_audio_clk_suspend()
401 priv->aud_pll_ctrl1 = readl(priv->mmio_base + SSPA_AUD_PLL_CTRL1); in mmp2_audio_clk_suspend()
412 writel(priv->aud_ctrl, priv->mmio_base + SSPA_AUD_CTRL); in mmp2_audio_clk_resume()
413 writel(priv->aud_pll_ctrl0, priv->mmio_base + SSPA_AUD_PLL_CTRL0); in mmp2_audio_clk_resume()
414 writel(priv->aud_pll_ctrl1, priv->mmio_base + SSPA_AUD_PLL_CTRL1); in mmp2_audio_clk_resume()
424 { .compatible = "marvell,mmp2-audio-clock" },
432 .name = "mmp2-audio-clock",