9  * scaling capabilities. MPLL rates are calculated as:
19 #include "clk-mpll.h"
79 	struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk);  in mpll_recalc_rate()  local
83 	sdm = meson_parm_read(clk->map, &mpll->sdm);  in mpll_recalc_rate()
84 	n2 = meson_parm_read(clk->map, &mpll->n2);  in mpll_recalc_rate()
95 	struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk);  in mpll_round_rate()  local
98 	params_from_rate(rate, *parent_rate, &sdm, &n2, mpll->flags);  in mpll_round_rate()
107 	struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk);  in mpll_set_rate()  local
111 	params_from_rate(rate, parent_rate, &sdm, &n2, mpll->flags);  in mpll_set_rate()
113 	if (mpll->lock)  in mpll_set_rate()
114 		spin_lock_irqsave(mpll->lock, flags);  in mpll_set_rate()
116 		__acquire(mpll->lock);  in mpll_set_rate()
119 	meson_parm_write(clk->map, &mpll->sdm, sdm);  in mpll_set_rate()
122 	meson_parm_write(clk->map, &mpll->n2, n2);  in mpll_set_rate()
124 	if (mpll->lock)  in mpll_set_rate()
125 		spin_unlock_irqrestore(mpll->lock, flags);  in mpll_set_rate()
127 		__release(mpll->lock);  in mpll_set_rate()
135 	struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk);  in mpll_init()  local
137 	if (mpll->init_count)  in mpll_init()
138 		regmap_multi_reg_write(clk->map, mpll->init_regs,  in mpll_init()
139 				       mpll->init_count);  in mpll_init()
142 	meson_parm_write(clk->map, &mpll->sdm_en, 1);  in mpll_init()
145 	if (MESON_PARM_APPLICABLE(&mpll->ssen)) {  in mpll_init()
147 			mpll->flags & CLK_MESON_MPLL_SPREAD_SPECTRUM ? 1 : 0;  in mpll_init()
148 		meson_parm_write(clk->map, &mpll->ssen, ss);  in mpll_init()
152 	if (MESON_PARM_APPLICABLE(&mpll->misc))  in mpll_init()
153 		meson_parm_write(clk->map, &mpll->misc, 1);  in mpll_init()
172 MODULE_DESCRIPTION("Amlogic MPLL driver");