574 	struct clk_onecell_data *clk_data;  in mtk_topckgen_init()  local
582 	clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);  in mtk_topckgen_init()
585 				    clk_data);  in mtk_topckgen_init()
588 				 clk_data);  in mtk_topckgen_init()
591 				    base, &mt7629_clk_lock, clk_data);  in mtk_topckgen_init()
593 	clk_prepare_enable(clk_data->clks[CLK_TOP_AXI_SEL]);  in mtk_topckgen_init()
594 	clk_prepare_enable(clk_data->clks[CLK_TOP_MEM_SEL]);  in mtk_topckgen_init()
595 	clk_prepare_enable(clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]);  in mtk_topckgen_init()
597 	return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);  in mtk_topckgen_init()
603 	struct clk_onecell_data *clk_data;  in mtk_infrasys_init()  local
605 	clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);  in mtk_infrasys_init()
608 			       clk_data);  in mtk_infrasys_init()
611 				  clk_data);  in mtk_infrasys_init()
614 				   clk_data);  in mtk_infrasys_init()
619 	struct clk_onecell_data *clk_data;  in mtk_pericfg_init()  local
628 	clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);  in mtk_pericfg_init()
631 			       clk_data);  in mtk_pericfg_init()
634 				    &mt7629_clk_lock, clk_data);  in mtk_pericfg_init()
636 	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);  in mtk_pericfg_init()
640 	clk_prepare_enable(clk_data->clks[CLK_PERI_UART0_PD]);  in mtk_pericfg_init()
647 	struct clk_onecell_data *clk_data;  in mtk_apmixedsys_init()  local
650 	clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);  in mtk_apmixedsys_init()
651 	if (!clk_data)  in mtk_apmixedsys_init()
655 			      clk_data);  in mtk_apmixedsys_init()
658 			       ARRAY_SIZE(apmixed_clks), clk_data);  in mtk_apmixedsys_init()
660 	clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMPLL]);  in mtk_apmixedsys_init()
661 	clk_prepare_enable(clk_data->clks[CLK_APMIXED_MAIN_CORE_EN]);  in mtk_apmixedsys_init()
663 	return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);  in mtk_apmixedsys_init()