Lines Matching refs:clk_data

614 	struct clk_onecell_data *clk_data;  in mtk_topckgen_init()  local
622 clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); in mtk_topckgen_init()
625 clk_data); in mtk_topckgen_init()
628 clk_data); in mtk_topckgen_init()
631 base, &mt7622_clk_lock, clk_data); in mtk_topckgen_init()
634 base, &mt7622_clk_lock, clk_data); in mtk_topckgen_init()
637 clk_data); in mtk_topckgen_init()
639 clk_prepare_enable(clk_data->clks[CLK_TOP_AXI_SEL]); in mtk_topckgen_init()
640 clk_prepare_enable(clk_data->clks[CLK_TOP_MEM_SEL]); in mtk_topckgen_init()
641 clk_prepare_enable(clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]); in mtk_topckgen_init()
643 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); in mtk_topckgen_init()
649 struct clk_onecell_data *clk_data; in mtk_infrasys_init() local
652 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); in mtk_infrasys_init()
655 clk_data); in mtk_infrasys_init()
658 clk_data); in mtk_infrasys_init()
661 clk_data); in mtk_infrasys_init()
672 struct clk_onecell_data *clk_data; in mtk_apmixedsys_init() local
675 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); in mtk_apmixedsys_init()
676 if (!clk_data) in mtk_apmixedsys_init()
680 clk_data); in mtk_apmixedsys_init()
683 ARRAY_SIZE(apmixed_clks), clk_data); in mtk_apmixedsys_init()
685 clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMPLL]); in mtk_apmixedsys_init()
686 clk_prepare_enable(clk_data->clks[CLK_APMIXED_MAIN_CORE_EN]); in mtk_apmixedsys_init()
688 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); in mtk_apmixedsys_init()
693 struct clk_onecell_data *clk_data; in mtk_pericfg_init() local
702 clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); in mtk_pericfg_init()
705 clk_data); in mtk_pericfg_init()
708 &mt7622_clk_lock, clk_data); in mtk_pericfg_init()
710 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); in mtk_pericfg_init()
714 clk_prepare_enable(clk_data->clks[CLK_PERI_UART0_PD]); in mtk_pericfg_init()