Lines Matching +full:jz4740 +full:- +full:rtc
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Ingenic JZ4740 SoC CGU driver
9 #include <linux/clk-provider.h>
14 #include <dt-bindings/clock/jz4740-cgu.h>
51 0x0, 0x1, -1, 0x3,
67 [JZ4740_CLK_RTC] = { "rtc", CGU_CLK_EXT },
71 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
96 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
98 CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1,
105 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
107 CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1,
114 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
116 CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1,
123 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
125 CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1,
132 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
134 CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1,
141 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
143 CGU_REG_CPCCR, 16, 1, 5, 22, -1, -1,
151 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
152 .div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 },
157 .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },
159 .div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 },
165 .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL, -1, -1 },
167 .div = { CGU_REG_SSICDR, 0, 1, 4, -1, -1, -1 },
173 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
174 .div = { CGU_REG_MSCCDR, 0, 1, 5, -1, -1, -1 },
180 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
181 .div = { CGU_REG_UHCCDR, 0, 1, 4, -1, -1, -1 },
187 .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },
189 .div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 },
193 /* Gate-only clocks */
197 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
203 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
209 .parents = { JZ4740_CLK_PCLK, -1, -1, -1 },
215 .parents = { JZ4740_CLK_PCLK, -1, -1, -1 },
221 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
227 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
233 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
239 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
261 CLK_OF_DECLARE_DRIVER(jz4740_cgu, "ingenic,jz4740-cgu", jz4740_cgu_init);