Lines Matching full:clk_ext1
69 …5m", "sys1_pll_800m", "sys3_pll_out", "sys1_pll_400m", "audio_pll2_out", "clk_ext1", "clk_ext4", };
72 "sys1_pll_40m", "audio_pll2_out", "clk_ext1", "clk_ext3", };
118 …nst imx8mq_pcie1_phy_sels[] = {"osc_25m", "sys2_pll_100m", "sys2_pll_500m", "clk_ext1", "clk_ext2",
128 …l1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext1", "clk_ext2", };
134 …l1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext1", "clk_ext2", };
147 …t imx8mq_enet_timer_sels[] = {"osc_25m", "sys2_pll_100m", "audio_pll1_out", "clk_ext1", "clk_ext2",
205 "sys3_pll_out", "clk_ext1", "sys1_pll_80m", "video_pll1_out", };
208 "sys3_pll_out", "clk_ext1", "sys1_pll_80m", "video_pll1_out", };
217 "sys1_pll_80m", "audio_pll1_out", "clk_ext1", };
258 …st char * const imx8mq_pcie2_phy_sels[] = {"osc_25m", "sys2_pll_100m", "sys2_pll_500m", "clk_ext1",
303 hws[IMX8MQ_CLK_EXT1] = imx_obtain_fixed_clk_hw(np, "clk_ext1"); in imx8mq_clocks_probe()