Lines Matching +full:imx8mm +full:- +full:ccm

1 // SPDX-License-Identifier: GPL-2.0
3  * Copyright 2017-2018 NXP.
6 #include <dt-bindings/clock/imx8mm-clock.h>
7 #include <linux/clk-provider.h>
38 /* CCM ROOT */
304 	struct device *dev = &pdev->dev;  in imx8mm_clocks_probe()
305 	struct device_node *np = dev->of_node;  in imx8mm_clocks_probe()
312 		return -ENOMEM;  in imx8mm_clocks_probe()
314 	clk_hw_data->num = IMX8MM_CLK_END;  in imx8mm_clocks_probe()
315 	hws = clk_hw_data->hws;  in imx8mm_clocks_probe()
325 	np = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-anatop");  in imx8mm_clocks_probe()
329 		return -ENOMEM;  in imx8mm_clocks_probe()
413 	np = dev->of_node;  in imx8mm_clocks_probe()
468 	 * DRAM clocks are manipulated from TF-A outside clock framework.  in imx8mm_clocks_probe()
612 					   hws[IMX8MM_CLK_A53_CORE]->clk,  in imx8mm_clocks_probe()
613 					   hws[IMX8MM_CLK_A53_CORE]->clk,  in imx8mm_clocks_probe()
614 					   hws[IMX8MM_ARM_PLL_OUT]->clk,  in imx8mm_clocks_probe()
615 					   hws[IMX8MM_CLK_A53_DIV]->clk);  in imx8mm_clocks_probe()
628 		uart_hws[i] = &hws[index]->clk;  in imx8mm_clocks_probe()
642 	{ .compatible = "fsl,imx8mm-ccm" },
650 		.name = "imx8mm-ccm",