Lines Matching +full:imx7d +full:- +full:ccm

1 // SPDX-License-Identifier: GPL-2.0-or-later
3  * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
6 #include <dt-bindings/clock/imx7d-clock.h>
10 #include <linux/clk-provider.h>
403 	clk_hw_data->num = IMX7D_CLK_END;  in imx7d_clocks_init()
404 	hws = clk_hw_data->hws;  in imx7d_clocks_init()
410 	np = of_find_compatible_node(NULL, NULL, "fsl,imx7d-anatop");  in imx7d_clocks_init()
875 					 hws[IMX7D_ARM_A7_ROOT_CLK]->clk,  in imx7d_clocks_init()
876 					 hws[IMX7D_ARM_A7_ROOT_SRC]->clk,  in imx7d_clocks_init()
877 					 hws[IMX7D_PLL_ARM_MAIN_CLK]->clk,  in imx7d_clocks_init()
878 					 hws[IMX7D_PLL_SYS_MAIN_CLK]->clk);  in imx7d_clocks_init()
884 	clk_set_parent(hws[IMX7D_PLL_ARM_MAIN_BYPASS]->clk, hws[IMX7D_PLL_ARM_MAIN]->clk);  in imx7d_clocks_init()
885 	clk_set_parent(hws[IMX7D_PLL_DRAM_MAIN_BYPASS]->clk, hws[IMX7D_PLL_DRAM_MAIN]->clk);  in imx7d_clocks_init()
886 	clk_set_parent(hws[IMX7D_PLL_SYS_MAIN_BYPASS]->clk, hws[IMX7D_PLL_SYS_MAIN]->clk);  in imx7d_clocks_init()
887 	clk_set_parent(hws[IMX7D_PLL_ENET_MAIN_BYPASS]->clk, hws[IMX7D_PLL_ENET_MAIN]->clk);  in imx7d_clocks_init()
888 	clk_set_parent(hws[IMX7D_PLL_AUDIO_MAIN_BYPASS]->clk, hws[IMX7D_PLL_AUDIO_MAIN]->clk);  in imx7d_clocks_init()
889 	clk_set_parent(hws[IMX7D_PLL_VIDEO_MAIN_BYPASS]->clk, hws[IMX7D_PLL_VIDEO_MAIN]->clk);  in imx7d_clocks_init()
891 	clk_set_parent(hws[IMX7D_MIPI_CSI_ROOT_SRC]->clk, hws[IMX7D_PLL_SYS_PFD3_CLK]->clk);  in imx7d_clocks_init()
894 	clk_set_parent(hws[IMX7D_GPT1_ROOT_SRC]->clk, hws[IMX7D_OSC_24M_CLK]->clk);  in imx7d_clocks_init()
896 	/* Set clock rate for USBPHY, the USB_PLL at CCM is from USBOTG2 */  in imx7d_clocks_init()
903 		uart_clks[i] = &hws[index]->clk;  in imx7d_clocks_init()
910 CLK_OF_DECLARE(imx7d, "fsl,imx7d-ccm", imx7d_clocks_init);