1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/clock/imx6ul-clock.h>
9 #include <linux/clk-provider.h>
106 	return of_machine_is_compatible("fsl,imx6ul");  in clk_on_imx6ul()
124 	clk_hw_data->num = IMX6UL_CLK_END;  in imx6ul_clocks_init()
125 	hws = clk_hw_data->hws;  in imx6ul_clocks_init()
136 	np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-anatop");  in imx6ul_clocks_init()
167 	clk_set_parent(hws[IMX6UL_PLL1_BYPASS]->clk, hws[IMX6UL_CLK_PLL1]->clk);  in imx6ul_clocks_init()
168 	clk_set_parent(hws[IMX6UL_PLL2_BYPASS]->clk, hws[IMX6UL_CLK_PLL2]->clk);  in imx6ul_clocks_init()
169 	clk_set_parent(hws[IMX6UL_PLL3_BYPASS]->clk, hws[IMX6UL_CLK_PLL3]->clk);  in imx6ul_clocks_init()
170 	clk_set_parent(hws[IMX6UL_PLL4_BYPASS]->clk, hws[IMX6UL_CLK_PLL4]->clk);  in imx6ul_clocks_init()
171 	clk_set_parent(hws[IMX6UL_PLL5_BYPASS]->clk, hws[IMX6UL_CLK_PLL5]->clk);  in imx6ul_clocks_init()
172 	clk_set_parent(hws[IMX6UL_PLL6_BYPASS]->clk, hws[IMX6UL_CLK_PLL6]->clk);  in imx6ul_clocks_init()
173 	clk_set_parent(hws[IMX6UL_PLL7_BYPASS]->clk, hws[IMX6UL_CLK_PLL7]->clk);  in imx6ul_clocks_init()
184 	 * Bit 20 is the reserved and read-only bit, we do this only for:  in imx6ul_clocks_init()
185 	 * - Do nothing for usbphy clk_enable/disable  in imx6ul_clocks_init()
186 	 * - Keep refcount when do usbphy clk_enable/disable, in that case,  in imx6ul_clocks_init()
480 	clk_set_rate(hws[IMX6UL_CLK_AHB]->clk, 99000000);  in imx6ul_clocks_init()
483 	clk_set_parent(hws[IMX6UL_CLK_PERIPH_CLK2_SEL]->clk, hws[IMX6UL_CLK_OSC]->clk);  in imx6ul_clocks_init()
484 	clk_set_parent(hws[IMX6UL_CLK_PERIPH]->clk, hws[IMX6UL_CLK_PERIPH_CLK2]->clk);  in imx6ul_clocks_init()
485 	clk_set_parent(hws[IMX6UL_CLK_PERIPH_PRE]->clk, hws[IMX6UL_CLK_PLL2_BUS]->clk);  in imx6ul_clocks_init()
486 	clk_set_parent(hws[IMX6UL_CLK_PERIPH]->clk, hws[IMX6UL_CLK_PERIPH_PRE]->clk);  in imx6ul_clocks_init()
489 	clk_set_rate(hws[IMX6UL_CLK_AHB]->clk, 132000000);  in imx6ul_clocks_init()
492 	clk_set_parent(hws[IMX6UL_CLK_PERCLK_SEL]->clk, hws[IMX6UL_CLK_OSC]->clk);  in imx6ul_clocks_init()
494 	clk_set_rate(hws[IMX6UL_CLK_ENET_REF]->clk, 50000000);  in imx6ul_clocks_init()
495 	clk_set_rate(hws[IMX6UL_CLK_ENET2_REF]->clk, 50000000);  in imx6ul_clocks_init()
496 	clk_set_rate(hws[IMX6UL_CLK_CSI]->clk, 24000000);  in imx6ul_clocks_init()
499 		clk_prepare_enable(hws[IMX6UL_CLK_AIPSTZ3]->clk);  in imx6ul_clocks_init()
502 		clk_prepare_enable(hws[IMX6UL_CLK_USBPHY1_GATE]->clk);  in imx6ul_clocks_init()
503 		clk_prepare_enable(hws[IMX6UL_CLK_USBPHY2_GATE]->clk);  in imx6ul_clocks_init()
506 	clk_set_parent(hws[IMX6UL_CLK_CAN_SEL]->clk, hws[IMX6UL_CLK_PLL3_80M]->clk);  in imx6ul_clocks_init()
508 		clk_set_parent(hws[IMX6UL_CLK_SIM_PRE_SEL]->clk, hws[IMX6UL_CLK_PLL3_USB_OTG]->clk);  in imx6ul_clocks_init()
510 		clk_set_parent(hws[IMX6ULL_CLK_EPDC_PRE_SEL]->clk, hws[IMX6UL_CLK_PLL3_PFD2]->clk);  in imx6ul_clocks_init()
512 	clk_set_parent(hws[IMX6UL_CLK_ENFC_SEL]->clk, hws[IMX6UL_CLK_PLL2_PFD2]->clk);  in imx6ul_clocks_init()
515 CLK_OF_DECLARE(imx6ul, "fsl,imx6ul-ccm", imx6ul_clocks_init);