Lines Matching refs:clk_hw_get_name

64 	pr_debug("%s pll %s\n", clk_hw_get_name(hw),  in xgene_clk_pll_is_enabled()
112 		 clk_hw_get_name(hw), fvco / nout, parent_rate,  in xgene_clk_pll_recalc_rate()
454 		pr_debug("%s clock enabled\n", clk_hw_get_name(hw));  in xgene_clk_enable()
462 			clk_hw_get_name(hw),  in xgene_clk_enable()
473 			clk_hw_get_name(hw),  in xgene_clk_enable()
494 		pr_debug("%s clock disabled\n", clk_hw_get_name(hw));  in xgene_clk_disable()
520 		pr_debug("%s clock checking\n", clk_hw_get_name(hw));  in xgene_clk_is_enabled()
523 		pr_debug("%s clock is %s\n", clk_hw_get_name(hw),  in xgene_clk_is_enabled()
546 			clk_hw_get_name(hw),  in xgene_clk_recalc_rate()
552 			clk_hw_get_name(hw), parent_rate, parent_rate);  in xgene_clk_recalc_rate()
585 		pr_debug("%s clock set rate %ld\n", clk_hw_get_name(hw),  in xgene_clk_set_rate()