Lines Matching refs:div_int
167 u32 div_int; member
415 u32 div_int, div_frc; in vc5_pll_recalc_rate() local
420 div_int = (fb[0] << 4) | (fb[1] >> 4); in vc5_pll_recalc_rate()
424 return (parent_rate * div_int) + ((parent_rate * div_frc) >> 24); in vc5_pll_recalc_rate()
431 u32 div_int; in vc5_pll_round_rate() local
440 div_int = rate / *parent_rate; in vc5_pll_round_rate()
441 if (div_int > 0xfff) in vc5_pll_round_rate()
449 hwdata->div_int = div_int; in vc5_pll_round_rate()
452 return (*parent_rate * div_int) + ((*parent_rate * div_frc) >> 24); in vc5_pll_round_rate()
462 fb[0] = hwdata->div_int >> 4; in vc5_pll_set_rate()
463 fb[1] = hwdata->div_int << 4; in vc5_pll_set_rate()
484 u32 div_int, div_frc; in vc5_fod_recalc_rate() local
493 div_int = (od_int[0] << 4) | (od_int[1] >> 4); in vc5_fod_recalc_rate()
498 if (div_int == 0 && div_frc == 0) in vc5_fod_recalc_rate()
502 return div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc); in vc5_fod_recalc_rate()
511 u32 div_int; in vc5_fod_round_rate() local
515 div_int = f_in / rate; in vc5_fod_round_rate()
521 if (div_int > 0xffe) { in vc5_fod_round_rate()
522 div_int = 0xffe; in vc5_fod_round_rate()
523 rate = f_in / div_int; in vc5_fod_round_rate()
531 hwdata->div_int = div_int; in vc5_fod_round_rate()
534 return div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc); in vc5_fod_round_rate()
547 hwdata->div_int >> 4, hwdata->div_int << 4, in vc5_fod_set_rate()